AN2061

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3 EEPROM EMULATION CONCEPT

3.1 Principle

Different concepts are described in the literature. Each of them rely on partitioning a bank of

the Flash into several Data-sets and on using control bits (per Flash bank and per Data-set)

to compute which Flash bank and which Data-set is the valid one. For variable-length Data-

sets, linked data-list structures should be considered.

The method described in this document is based on fixed-length Data-sets and 2 Flash banks.

Variable update frequency

The variable update frequency may set high requirements on the program / erase cycle of the

Flash and on the Flash features (ex: Read-While-Write). Those features are analysed in de-

tails in the following pages.

3.2 Program/erase cycle

The requirements on program / erase cycles are computed by dividing the needed number of

erase cycles by the total number of Data-sets in the Flash banks (example with Figure 1: n+m).

When this number is still higher than the Flash write/erase endurance characteristics, a closer

analysis is needed to understand when the Data-sets are updated:

– when Data-sets need to be updated during operation, it is proposed to use a buffer in RAM

and to save the data before shutting-down the microcontroller.

– when Data-sets are updated only before power-down sequence, it is proposed to increase

the size of the Flash bank or to use a 3rd bank (see additional information in Chapter 4).

Figure 1. Bank partitioning for emulated EEPROM

Area for

status bit storage

Area for

Data-set storage

(Data-set bits and

ST10F2xx Flash bank-x

Data-set-0

Data-set-1

Data-set-n

Data-set-2

Status bits for

Data-set-n

0

n

1

2

ST10F2xx Flash bank-y

Data-set-0

Data-set-1

Data-set-m

Data-set-2

0

m

1

2

switch between each bank

(erase one when using the other)

Flash bank bits)