APPENDIX

Low-consumption modes management

The application board is not provided with the circuits that handle the loads in a monitor SMPS during Suspend

and OFF modes. As a result, if the board is connected to a monitor unit "as is", the consumption from the mains

will be significantly higher than the values shown in tables 5 and 6. In particular, it will not be possible to meet

the "less than 3W" specification required by the current energy saving regulations in OFF mode.

This happens because the monitor’s circuits, in particular those connected to the high voltage buses, are

still powered and have some mA residual consumption, despite they are not operating. The actual load

is then heavier than the one assumed in table 5 and 6, where the load conditions in OFF-mode are

simulated, provided some "power management" circuit takes care of their reduction.

A popular solution used for cutting down the residual loads and minimizing the power consumption in

OFF mode is to reduce 8 to 10 times the voltage of all of the outputs, except the one that powers the

µP

governing the entire monitor operation, power management included.

In this way the voltage produced by the SMPS will not be enough to power monitor’s circuits and their

consumption will drop to zero. Additionally, the reflected voltage during switch OFF-time will be much

lower, which will reduce switching and capacitive losses.

The above mentioned functionality can be achieved in a number of different ways. Figure A1 shows the

application board schematic modified with the addition of a circuit (pointed out by the shaded areas) that

does the job. A 5V linear regulator (L7805CP), which is supposed to supply the

µP, has been added for

completeness. The operation of the circuit can be described as follows.

When the OFF signal is pulled high, Q5 is turned on, the base of Q4 is grounded and Q4 is turned on as

well. This connects the 80V winding and the 2.2

µF capacitor, charged at 80V, to C17+C19 charged at

15V. Being the latter much bigger, the transient voltage change is negligible. The 4.7

Ω resistor in series

to Q4’s emitter limits the current surge during the transient.

By turning Q5 on, the cathode of the TL431, typically at 11V in normal operation, is now forced to drop at

about 4V by the 3.3V zener and the decoupling diode. Considering 1V drop across the photodiode and

the drop on R26, which changes very little, the voltage on C17+C19 will be fixed at about 8.5V. The

volts-per-turn across the windings will drop from 80 / 32 = 2.5 V/turn to 8.5/32 = 0.265 V/turn, that is

nearly 10 times less. All of the outputs will be reduced by the same ratio (a higher value can be found

because of capacitors peak charging due to load absence). The TL431 is cut out: it sees the drop of the

200V output and would try to correct this by increasing its cathode voltage, which is not possible be-

cause this is fixed by the 3.3V zener.

The reduction of winding voltages concerns the primary side as well: the voltage generated by the auxil-

iary winding drops to some 1V and is no longer able to power the L5991. To maintain circuit operation, a

second auxiliary winding, stacked on the first one, has been added, with a turn number (40) such that in

OFF mode it develops a voltage sufficient to power the L5991.

However, during normal operation the voltage it develops will be much higher (close to 120V). This is

why Q6 has been added: during normal operation the first auxiliary winding develops more than 15V

thus the base-emitter junction of Q6 is reverse biased and Q6 is cut off, thus blocking the high voltage.

When entering OFF mode, Q6 is turned on (it does not work as a linear regulator) and lets the second

auxiliary winding supply the L5991.

As Q5 is turned off because normal operation is to be resumed, also Q4 will be turned off and the output

voltages will go back to their rated values after a transient similar to the initial power-up.

Table A1 shows the improvement offered by the voltage reduction circuit. A load condition similar to or

slightly heavier than that of a real monitor (without any power management circuit) is assumed. The con-

sumption from the mains is shown with and without the additional circuit included in fig. A1.

Table A1. Consumption from the mains in OFF mode.

88

110

160

220

264

Pin [W]

(*)

4.3

4.4

4.6

4.8

4.9

Pin [W]

(**)

2

2.1

2.2

2.4

2.5

Load conditions: 200V: 40 k

Ω; 80V: 20 kΩ; +5V: 47Ω; other outputs open

(*) Without voltage reduction

(**) With voltage reduction

AN1132 APPLICATION NOTE

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