AN2281 datasheet(9/38 Pages) STMICROELECTRONICS

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AN2281

Implementation on the ST7LITE35 microcontroller

9/38

3.2

Lite timer for measuring the rotor speed

3.2.1

Block diagram and functional description

The Lite timer (LT) can be used for general-purpose timing functions. It is based on two free-

running 8-bit upcounters and one 8-bit input capture register.

Figure 6 shows the Lite timer block diagram.

Figure 6.

The Lite timer block diagram

After an MCU reset, counter 1 starts incrementing from 0 at a frequency of fOSC/32. An

overflow event occurs when the counter rolls over from F9h to 00h. If fOSC=8 MHz, then the

time period between two counter overflow events is 1 ms. This period can be optionally

doubled by setting the TB bit in the LTCSR1 register.

When Counter 1 overflows, the TB1F bit is set by hardware and an interrupt request is

generated if the TB1IE bit is set.

The Counter 2 functions in a similar way to Counter 1 but, after an MCU reset, it increments

starting from the value stored in the LTARR register instead of starting from 0.

As you can see in Figure 6, Counter 1 is associated with an 8-bit input capture register, used

to latch the free-running upcounter after a rising or falling edge is detected on the LTIC pin.

LTCSR1

8-bit TIMEBASE

8-bit

fLTIMER

LTIC

fOSC/32

TB1F

TB1IE

ICF

ICIE

LTTB1 INTERRUPT REQUEST

LTIC INTERRUPT REQUEST

LTICR

INPUT CAPTURE

1 or 2 ms

Timebase

(@ 8MHz

fOSC)

To 12-bit AT TImer

fLTIMER

LTCSR2

TB2F

TB2IE

LTTB2

8-bit TIMEBASE

8-bit AUTORELOAD

LTCNTR

LTARR

COUNTER 2

COUNTER 1

Interrupt request

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