AN2419

Clocks

13/22

The AHB and APB prescalers allow you to choose the AHB and APB frequencies from a

wide range of possibilities:

●

HCLK (AHB Clock) can be generated from CK_SYS divided by 1, 2, 4 or 8

●

PCLK (APB Clock) can be generated from HCLK divided by 1, 2, 4, 8 or 16

The clock provided to the Timers (CK_TIM) can have twice or the same frequency as PCLK.

This allows the timers to count at high frequency (up to 64MHz)

Table 1 gives some typical clock configurations:

Table 1.

Typical prescaler uses

The software must respect the configuration constraints of the PLL.

2.6

Clock-out capability: MCO (Main Clock Output)

The Main Clock Output (MCO) capability allows you to output a clock on the external MCO

pin. The configuration registers of corresponding GPIO port must programmed in alternate

function mode. You can select one of 4 clock signals as MCO clock.

●

CK_PLL2

●

HCLK

●

PCLK

●

CK_OSC4M

The selection is controlled by the MCOS[1:0] bits of CLKCTL register. A dedicated prescaler

(divide by 1 or 2, selected by MCOP bit) can be applied to this clock before outputting it to

the MCO pin. Care must be taken when switching MCO clock selection, the alternate

function should be disabled to avoid any glitches on the MCO pin.

2.7

Clock detector (CKD)

A CKD (Clock Detector) is implemented to:

●

detect if no clock is present on OSC4M (broken or disconnected resonator) and prevent

the software from selecting it.

●

automatically feeds the MCU with the FREEOSC used as emergency clock if no clock

is detected.

●

generate an interrupt if enabled, allowing the MCU to perform some rescue operations

For more detail see the Reference Manual (UM0191).

(MHz)

PLL

Factor

(MHz)

HPRESC

[1:0]

(MHz)

PPRESC

[1:0]

(MHz)

PPRESC2

(MHz)

(MHz)

4

x16

64

00

64

00

64

1

32

48

01

32

16

x15

60

00

60

00

60

30

x14

56

00

56

00

56

28

x12

48

00

48

00

48

24

x16

64

01

32

00

32

16