AN2647 datasheet(25/34 Pages) STMICROELECTRONICS

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AN2647

Interfacing with synchronous memory

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EMI bus configuration for asynchronous mode

Table 8 shows the EMI bus registers and control bits that are required for the STR91xFA to

access the PSRAM in asynchronous mode. The burst mode parameters are included in the

table but are not don't cares in asynchronous mode

The key parameters that you have to configure are:

BCLK clock frequency, which is set to 80 MHz to match the MT45W4M's maximum

clock rate. Note the BCLK pin is disabled in asynchronous mode.

Select the EMI_WEn, EMI_UBn, EMI_LBn signals for 16-bit write

Set EMI_RDn timing (WSTRD=5, WSTOEn=4), EMI_WEn timing (WSTWR=5,

WSTWEn=0). The read and write timings should meet the MT45W4M's 70 ns access

time.

Set EMI_ALE to 2 tBCLK wide and active low.

Configure Port5,6, 7, 8 and 9 as EMI bus port. Set Port 6 pin P6.0 as CRE output and

Port 5 pin P5.1 as CS1 chip select.

Table 8.

EMI and port register configuration for PSRAM async mode (80 MHZ BCLK)

EMI configuration

Multiplexed 16-bits asynchronous mode

Bit

Name

Bit value

Function

EMI_BCRx (maintain

reserved bits' default

value)

19:18

BWLEN

Burst write transfer length

SYNCWRITEDEV

Asynchronous write device

BMWrite

Burst mode write disabled

11:10

BRLEN

Burst read transfer length

SYNCREADDEV

asynchronous read device

BPM

Normal mode (non burst or page mode)

5:4

16-bit data bus width

Bank not write protected

BLE

Byte Lane Enable

EMI_RCR

4:0

WSTRD

101

Read Wait State = 5

70 ns PSRAM access time

EMI_OECR

3:0

WSTOEN

100

EMI_RDn assertion delay = 4

EMI_WCR

4:0

WSTWR

101

Write Wait State = 5

EMI_WECR

3:0

WSTWEN

000

EMI_WRn assertion delay = 0

EMI_ICR

3:0

IDCY

011

Idle Cycle = 3 BCLK

EMI_BRDCR

4:0

WSTBRD

000

Burst read wait state= 0

SCU_EMI

BYTE_EN

Enable EMI_UBn and LBn signals

BCLK_EN

Disable BCLK output

GPIOEMI

Set Port 8/9 as EMI bus

SCU_CLKCNTR

18:17

EMIRatio

BCLK=HCLK (80 MHz)

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