AN3265

Software description

Doc ID 17860 Rev 1

9/19

2

Software description

The application software does not use STM8S standard firmware library. It rather consists in

optimized code with direct register accesses to control and use the general purpose

peripherals as described in Section 2.1.

2.1

STM8S peripheral configuration

2.1.1

WWDG

The WWDG peripheral is used for software monitoring (see Figure 3). The refresh period

and the illegal refresh window duration are defined by the user. The microcontroller is reset

when the WWDG counter is not refreshed by the end of the refresh period or if it is refreshed

during the illegal refresh window.

In this particular example, the WWDG resets the STM8S because of a user simulated

software failure causing the WWDG counter not to be refreshed in time. As it depends on

the MCU clock, the WWDG is useless when a hardware failure, such as an MCU clock

failure, occurs.

Figure 3.

WWDG software monitoring

2.1.2

Clock security system (CSS)

The Clock Security System (CSS) monitors HSE crystal clock source failures. When the

or disconnected resonator (or for any other reason), the clock controller activates a stall safe

recovery mechanism by automatically switching the master clock to the auxiliary clock

microcontroller is reset.

2.1.3

IWDG

The IWDG peripheral is used to monitor software and hardware failures. Its counter is

refreshed by the application. The microcontroller is reset if the IWDG counter is not

refreshed in time because a hardware failure occurred.

In this particular example, the IWDG monitors the HSE clock failure when the CSS is

disabled since it is clocked by the 128 kHz LSI internal RC clock source which remains

active in case of master clock failure.

time

WWDG refresh period

Refresh not

allowed

Refresh window