PM0020 datasheet(62/87 Pages) STMICROELECTRONICS

62 / 87 page

ISC logic description

PM00020

62/87

12.3

Configuration bits

Except for the Security bit, you can read the rest of the configuration bits by shifting out the

content of the Configuration register. As for the Security bit, you can read this through either

the Default register or the Instruction register. Detailed information on how to read these bits

is given in Section 12.4: Register description

ISC_PROGRAM

ISC-Data

CSU

••

•

ISC_PROGRAM_SECURITY

ISC_Default

••

•

ISC_PROGRAM_UC

Usercode

CSU

••

•

ISC_ERASE

ISC_Sector

CSU

••

ISC_READ

ISC_Data

CSU

••

•

ISC_BLANK_CHECK

ISC_Sector

CSU

••

•

ISC_TEST_ENABLE

Test_Enable

••

Table 30.

Instruction set (continued)

Instruction

Origin

Mode

Secure

CSx Mapping

0: CS0 is mapped to Main Flash and CS1 is mapped to Secondary Flash.

1: CS0 is mapped to Secondary Flash and CS1 is mapped to Main Flash

LVD_th

0: The LVD threshold is set to 2.4 V.

1: The LVD threshold is set to 2.7 V

LVD_RESET_SELECT

0: LVD Reset Out is generated by VDD input only.

1: LVD Reset Out is generated by VDD or VDDQ input

LVD_RESET_WARNING

0: Early Warning is generated by VDD input only.

1: Early Warning is generated by VDD or VDDQ inputs

Security

0: The device is not secured. JTAG port can read Flash memory.

1: The device is secured and Flash memory content can not be read by JTAG. When this bit is set,

the device sets DEBUG_EN output to low which disables the ARM MCU JTAG port

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