PM0020 datasheet(64/87 Pages) STMICROELECTRONICS

64 / 87 page

ISC logic description

PM00020

64/87

12.4.2

ISC default register

765

432

N/A

SECURITY

INT_ERROR

MODE

READY/BUSY

ISC_ERROR

Bit 7

N/A

Bit 6

SECURITY: Security bit (Readout protection).

0: Unsecured device.

1: Secured device.

Bits 5:4

INT_ERROR: Internal Erase/Program Error

00: N/A

01: Fail

10: Success (default)

11: N/A.

These bits will indicate an error if:

1. An attempt to read, program, or erase is made when the Flash is secured

(SECURITY =1).

2. An attempt to program the OTP Sector is made while the OTP LOCK bit is set

(OTP_LOCK_BIT = 1)

3. When the Flash reports an erase/program error.

4. When an ISC_DISABLE instruction is issued and the ISC is in busy mode.

It is not mandatory to clear an INT_ERROR flagged by an internal ERASE or

PROGRAM operation. The device will continue to function normally. However,

the error flag will remain in the ISC_Default and the Instruction_Register bits

<5:4>.

If an INT_ERROR is issued, it can be cleared by a Test-Logic-Reset, a VCC

power-down or an ISC_CLR_STATUS instruction.

Note: If a Test-Logic-Reset is issued while ISC is in busy mode no error flag is

set.

Bit 3

MODE: Mode status bit

0: PSD mode

1: ISC mode

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