RM0319 datasheet(287/368 Pages) STMICROELECTRONICS

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RM0319

JPEG codec accelerator (JPGC)

Doc ID 022640 Rev 3

287/368

JPEG codec accelerator (JPGC)

This chapter focuses on JPEG functionality and operation.

For technical details about the programmable registers related to the JPEG, refer to the

JPEG registers in the following companion document:

●

RM0321: SPEAr320S address map and registers

26.1

Overview

The JPEG Codec present in SPEAr320S is built around the existing JPEG ECS CODEC

and extends its functionality by providing additional support for JPEG header parsing and

generation. The encoding process compresses 8x8 pixel blocks (data units) into either a

complete JPEG encoded output stream or only ECS data depending on whether the header

processing functionality of the core is enabled. The decoding process can either decode a

complete JPEG encoded data stream or an input data stream with only ECSs. In either

case, the core decodes the ECS data into valid 8 x 8 pixel blocks (data units).

26.2

Main features

●

Compliance with the baseline JPEG standard (ISO/IEC 10918-1)

●

Single-clock per pixel encoding/decoding

●

Support for up to four channels of component color

●

8 bit/channel pixel depths

●

Programmable quantization tables (up to four)

●

Programmable Huffman tables (two AC and two DC)

●

Programmable Minimum Coded Unit (MCU)

●

Configurable JPEG headers processing

●

Support for restart marker insertion

●

Use of two DMA channels (from the basic subsystem) and of two 8 x 32-bit FIFO’s

(local to the JPGC) for efficient transferring and buffering of encoded/decoded data

from/to the Codec Core.

26.3

Pins

The JPGC directly interfaces with the signals summarized in Table 86. The JPGC is

connected as a slave on the AHB bus, and has two DMA channels asserted to itself. A

functional diagram of these signal interfaces is given in Figure 101.

Table 86.

GPIO signal interface

Group

Signal name

Direction

Size

(bit)

Description

AHB Slave

Input/Output -

See AMBA specification.

DMAC

Input/Output -

See Chapter 36: DMA controller (DMAC)

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