RM0319 datasheet(294/368 Pages) STMICROELECTRONICS

294 / 368 page

Digital audio port (I2S)

RM0319

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Doc ID 022640 Rev 3

27.6

Interrupts

The four I2S interrupt sources are ORed to a single global interrupt request. The I2S global

interrupt is mapped on the same interrupt request line (IRQ30) as the PL_GPIO interrupt

request.

Note:

PL_GPIO interrupts must be disabled if I2S interrupts are used and vice versa.

See also: Interrupt request table on page 361

27.7

Programming examples

27.7.1

Using the I2S transmitter (Tx mode)

Note:

Before executing the following steps, enable the I2S block clocks.

Enable I2S: write IER[0] = 1

Fill TX FIFOs: write data to LTHR and RTHR until filled.

Alternately, use the TXDMA registers to write data into the TX FIFOs.

Enable the transmitter block: write ITER[0] = 1

Enable clock generation: write CER[0] = 1

27.7.2

Using the I2S receiver (Rx mode)

Enable I2S: write IER[0] = 1

Enable the receive block: write IRER[0] = 1

Read data through the LRBR and RRBR/RXDMA registers.

Table 88.

I2S interrupts

Name

Interrupt

Description

intr_emp_tx

Tx block empty

This interrupt is asserted when the empty trigger threshold level for the TX

FIFO is reached. A TX FIFO Empty interrupt is cleared by writing data to the

TX FIFO to bring its level above the empty trigger threshold level for the

channel

intr_or_tx

Tx block overrun

This interrupt is asserted when an attempt is made to write to a full TX. A

Data Overrun interrupt is cleared by reading the Transmit Channel Overrun

(TXCHO) bit [0] of the Transmit Overrun Register (TOR0). FIFO (any data

being written is lost while data in the FIFO is preserved).

intr_da_rx

Rx block data available

This interrupt is asserted when the trigger level for the RX FIFO is reached.

This interrupt is cleared by reading data from the RX FIFO until its level

drops below the data available trigger level for the channel.

intr_or_rx

Rx block overrun

This interrupt is asserted when an attempt is made to write received data to

a full RX FIFO (any data being written is lost while data in the FIFO is

preserved). This interrupt is cleared by reading the Receive Channel

Overrun (RXCHO) bit [0] of the Receive Overrun Register (ROR0).

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