RM0319 datasheet(340/368 Pages) STMICROELECTRONICS

340 / 368 page

Reconfigurable array subsystem (RASCFG)

RM0319

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Doc ID 022640 Rev 3

Reconfigurable array subsystem (RASCFG)

This chapter provides a general introduction the RAS subsystem and programming the RAS

registers.

For further technical details about the RASCFG registers, refer the following companion

document:

●

RM0321: SPEAr320S address map and registers

32.1

Overview

The SPEAr320S reconfigurable array subsystem includes the following interfaces:

●

FSMC: NAND Flash interface (8/16 bits, 4 chip selects) (see Section 8: Parallel NAND

Flash controller (FSMC))

●

EMI: External memory interface (16 data bits, 24 address bits and 4 chip selects) (see

Section 9: External memory interface (EMI))

●

CAN0, CAN1: 2 x CAN2.0 interfaces (see Section 15: Controller area network ports

(CAN))

●

MACB: 2 x Ethernet MAC modules with 1 MII or 2 RMII interfaces (see Section 13: Fast

Ethernet ports (RMII0/RMII1/MII1))

●

UART1, 2, 3, 4, 5, 6: 6 x UARTs with SW flow control (baud rate up to 7 Mbps) (see

Section 16: Asynchronous serial ports (UART))

●

UART_RS485: UART/RS485 interface (see Section 16: Asynchronous serial ports

(UART))

●

CLCD: LCD interface (up to 1024x768, 24 bits LCD controller, TFT and STN panels)

(see Section 24: LCD display controller (CLCD)

●

TOUCHSCREEN: Touchscreen block (see Section 25: Touchscreen interface

(TOUCHSCREEN)))

●

SSP1,2: 2 x independent SPI ports (see Section 18: Synchronous serial ports (SSP))

●

PL-GPIO: PL_GPIOs with interrupt capabilities (see Section 23: Extended general

purpose I/O (PL_GPIO)

●

Memory Card Controller: SD/SDIO/MMC interface supporting SPI, SD1, SD4 and

SD8 mode (see Section 14: MMC-SD card/SDIO controller)

●

SPP: Standard parallel port (SPP device implementation) (see Section 20: Legacy

IEEE 1284 parallel port (SPP))

●

PWM: Up to 4 PWM outputs (see Section 38: Pulse width modulators (PWM)

●

I2C1,2: 2 x I2C interfaces (see Section 17: I2C bus ports (I2C))

●

I2S: I2S input-output for voice or modem interfaces (see Section 27: Digital audio port

(I2S)

32.2

I/O multiplexing scheme configuration

The RASCFG registers are used to select the I/O multiplexing scheme as described in the

datasheet pin description tables.

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