RM0319 datasheet(344/368 Pages) STMICROELECTRONICS

344 / 368 page

Vectored interrupt controller (VIC)

RM0319

344/368

Doc ID 022640 Rev 3

33.3

Functional description

Figure 114 shows the block diagram of VIC.

Figure 114. VIC block diagram

33.3.1

Interrupt request logic

The interrupt request logic block receives the interrupt requests from peripherals and

combines them with the software interrupt requests (see Section 33.3.6). After that, it masks

out the requests that are not enabled (through the VICINTENABLE register) and routes the

others to either IRQSTATUS or FIQSTATUS depending on VICINTSELECT.

FIQ interrupts have the highest priority, followed by vectored interrupts (0-15) and, finally,

non vectored interrupts.

33.3.2

Non-vectored FIQ interrupt logic

The non-vectored FIQ interrupt logic block generates the FIQ interrupt signal by combining

the FIQ interrupt requests coming from the interrupt request logic and any requests from

daisy-chained interrupt controllers.

VICINTSOURCE[31:0]

nVICRQIN

VICVECTADDRIN

nVICFIQIN

VICVECTADDROUT

HRESP[1:0]

HCLK

HSELVIC

HRESETn

HWRITE

HREADYIN

HREADYOUT

nVICFIQ

nVICIRQ

HTRANS

HADDR[11:2]

HRDATA[31:0]

HWDATA[31:0]

HSIZE[2:0]

HPROT

FIQSTATUS

[31:0]

IRQSTATUS

[31:0]

Interrupt

request

logic

IRQ

Daisy

Chain

IRQ

vector

address

and

priority

logic

Non-vectored IRQ

interrupt logic

VectAddrIn

VectAddrOut

AHB slave

interface

Control logic

Non-vectored FIQ

interrupt logic

IRQ0

VectAddr0

IRQ1

IRQn

IRQ15

VectAddr1

VectAddrn

VectAddr15

Vector interrupt 0

Vector interrupt 1

Vector interrupt 15

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