RM0319 datasheet(345/368 Pages) STMICROELECTRONICS

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RM0319

Vectored interrupt controller (VIC)

Doc ID 022640 Rev 3

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33.3.3

Non-vectored IRQ interrupt logic

The non-vectored IRQ interrupt logic block generates the non-vectored IRQ interrupt signal

by combining the non-vectored IRQ interrupt requests coming from the interrupt request

logic. This signal is then sent to the IRQ vector address and priority logic.

33.3.4

Vectored interrupts

As depicted in Figure 114, there are 16 vectored interrupt blocks within the VIC. Each

vectored interrupt block receives the IRQ interrupt requests from the interrupt request logic

block and generates a vectored IRQ interrupt.

In particular, a vectored IRQ interrupt is generated only if:

●

It is enabled in the VICINTENABLE register.

●

It is set to generate an IRQ interrupt in the VICINTSELECT register.

●

It is enabled in the relevant VICVECTCNTL register.

●

It is currently the highest requesting interrupt (vector 0 to vector 15, highest to lowest).

Besides, each vectored interrupt block is associated to the 32-bit address of the ISR to be

executed. These ISR addresses are mapped in the VICVECTADDRi (with i = 0...15)

registers. The VICVECTADDR register contains the ISR address for the currently active IRQ

interrupt.

33.3.5

Interrupt priority logic

The interrupt priority logic block organizes the following requests according to their priority:

●

Non-vectored interrupt requests

●

Vectored interrupt requests

●

External interrupt requests

If the interrupt is not currently being serviced, the highest priority request generates an IRQ

interrupt.

Note:

External interrupt is not being used in SPEAr320S.

33.3.6

Software interrupts

The software can control the source interrupt lines to generate software interrupts

(VICSOFTINT register). These interrupts are generated before interrupt masking within the

interrupt request logic block, in the same way as external source interrupts.

It is possible to clear software interrupts by writing to the VICSOFTINTCLEAR register. This

is normally done at the end of the ISR.

33.3.7

AHB slave interface

The AHB slave interface block connects the VIC to the CPU through the AHB bus.

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