UM0851 datasheet(43/245 Pages) STMICROELECTRONICS

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UM0851

Communication device drivers

Doc ID 16604 Rev 2

43/245

Communication device drivers

All the devices in the SPEAr embedded MPU family provide a rich set connectivity functions

and have embedded controllers for various low speed and high speed standard buses.

This section describes all the communication-oriented SPEAr drivers.

4.1

GMAC Ethernet driver

Ethernet is a family of standard technologies widely used in local area networks (LAN). All

SPEAr devices have an embedded GMAC Ethernet controller. While SPEAr600 supports

gigabit Ethernet operations, the SPEAr3xx family GMAC is hard-configured to support only

fast Ethernet. This section describes the GMAC Ethernet driver.

4.1.1

Hardware overview

Within its high-speed (HS) connection subsystem, SPEAr provides a Synopsys's DWC

Ether MAC 10/1000/1000 Univ. able to transmit and receive data over Ethernet in

compliance with the IEEE 802.3-2002 standard. The GMAC controller is equipped with a

AHB master interface (DMA), for transferring Ethernet frames to/from the system memory,

and a AHB 32-bit slave interface to access the GMAC subsystem's control & status

registers. It supports the following modes:

●

MII (media independent interface) for 10/100 Mbps operation.

●

GMII interface for gigabit (1000Mbps) operation (only in SPEAr600)

The transmit FIFO (TxFIFO) buffers the data read from the system memory by the DMA

before their transmission by the GMAC core. Similarly, the receive FIFO (RxFIFO) stores the

Ethernet frames received from the line until they are transferred to the system memory by

the DMA. These are asynchronous FIFOs, as they also transfer data between the

application clock and the GMAC line clocks. Both FIFOs are implemented in 35-bit wide

dual-ported RAM : TxFIFO is 2 Kbytes deep while RxFIFO is 4 Kbytes deep.

UM0851 Datasheet(PDF) 43 Page - STMicroelectronics