AN4570 datasheet(7/46 Pages) STMICROELECTRONICS

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AN4570

Overview of the STM32F30xxD/E flexible static memory controller

Figure 2. FMC memory banks

1.1

Interfacing asynchronous static memories (NOR Flash,

SRAM)

The interface signals are synchronized by the internal clock HCLK. This clock is not output

to the memory

The FMC always samples the data before de-asserting the chip select signal NE. This

guarantees that the memory data-hold timing constraint is met (chip enable high to data

transition, usually 0 ns min.).

•

If extended mode is enabled (EXTMOD: bit is set in the FSMC_BCRx register), there

are up to four extended modes (A, B, C and D) and it is possible to mix modes A, B, C

and D in read and write access. For example, read operation can be performed in

mode A and write in mode B.

•

If Extended mode is disabled, the FMC operates in Mode1 or Mode2 as follows:

–

Mode 1 is the default mode when SRAM/ PSRAM memory type is selected

(Bits 3:2 MTYP = 0x0 or 0x01 in the FSMC_BCRx register).

–

Mode 2 is the default mode when NOR memory type is selected

(Bits 3:2 MTYP = 0x10 in the FSMC_BCRx register).

Table 2. FMC operating modes

Asynchronous mode

Memory type

SRAM/PSRAM

NOR

Extended mode disabled

Mode 1

Mode2

Extended mode enabled

Mode A

Mode B, C, D

AN4570 Datasheet(PDF) 7 Page - STMicroelectronics