AN4570 datasheet(5/46 Pages) STMICROELECTRONICS

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AN4570

Overview of the STM32F30xxD/E flexible static memory controller

Overview of the STM32F30xxD/E flexible static

memory controller

The FMC has the following main features:

•

Interface with static-memory mapped devices including:

–

Static random access memory (SRAM),

–

NOR Flash memory/OneNAND Flash memory,

–

PSRAM (4 memory banks),

–

16-bit PC Card compatible devices,

–

Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbyte of

data

•

Supports burst mode access to synchronous devices (NOR Flash and PSRAM)

•

8- or 16-bit wide data bus

•

Independent chip select control for each memory bank

•

Independent configuration for each memory bank

•

Programmable timings to support a wide range of devices, in particular:

–

Programmable wait states (up to 15)

–

Programmable bus turnaround cycles (up to 15)

–

Programmable output enable and write enable delays (up to 15)

–

Independent read and write timings and protocol, so as to support the widest

variety of memories and timings

•

Write enable and byte lane select outputs for use with PSRAM and SRAM devices

•

Translation of 32-bit wide AHB transactions into consecutive 16-bit or 8-bit accesses to

external 16-bit or 8-bit devices

•

The FMC embeds two Write FIFOs:

–

Write Data FIFO with 16x33-bit depth,

–

Write Address FIFO with 16x30-bit depth).

•

External asynchronous wait control

The FMC registers that define the external device type and associated characteristics are

usually set at boot time and do not change until the next reset or power-up. However, it is

possible to change the settings at any time.

Figure 1 illustrates the FMC block diagram.

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