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STC5423 Datasheet(PDF) 13 Page - Connor-Winfield Corporation |
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STC5423 Datasheet(HTML) 13 Page - Connor-Winfield Corporation |
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13 / 60 page ![]() Page 13 of 60 TM114 Rev:1.4 Date: October 24, 2011 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5423 Synchronous Clock for SETS Data sheet Clock Output Jitter Note 2: Filter bandwidth is from 12kHz to Frequency/2 Table 6: Clock Output Jitter Clock Output Frequency RMS jitter2 (Typical) pk-pk jitter2 (10-12) (Typical) (MHz) (ps) (ps) (UI) CLK1/CLK2 (LVPECL/LVDS) 156.25 13 210 0.03 155.52 13 210 0.03 125 13 210 0.03 77.76 13 210 0.02 CLK3~CLK7 (LVCMOS) 77.76 19 330 0.03 38.88 16.5 280 0.01 19.44 15 230 0.005 25 13 180 0.005 2.048 11 180 0.0004 1.544 11 160 0.0003 |
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