STC5423 datasheet(39/60 Pages) CONNOR-WINFIELD

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TM114

Rev:1.4

Date: October 24, 2011

STC5423

Synchronous Clock for SETS

Data sheet

SRCSW_States, 0x1E (R)

Indicates status of pin SRCSW.

0 = Low, 1 = High

T0/T4_Tag_Select, 0x1F (R/W)

Selects between timing generator T0 and T4 for the sharing registers 0x20~0x3F.

0 = T0; 1 = T4

Default value: 0

Control_Mode, 0x20 (R/W)

Mode control bits for individual timing generator. Select between timing generator T0 and T4 at the register T0/

T4_Tag_select (0x1F).

Phase_Align (T0 timing generator only)

Determines the phase relationship is arbitrary or frame phase align.

0 = Arbitrary; 1 = Align (Frame phase align is only enabled when frequency of reference input is at

8kHz)

Internal Test

0 = Normal operation; 1 = Reserved

HO_Usage

Determines which holdover history is used.

0 = Device Holdover History (DHH); 1 = User specified history

Revertive

Selects the revertive mode or non-revertive mode of the auto-elector.

0 = Non-revertive; 1 = Revertive

Ref_Sel_Mode

Determines reference selection mode.

0 = Manual; 1 = Auto

This bit may be overridden by bit Hard_Wired_Switch of this register.

OOP

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x1E

Not used

Pin Status

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x1F

Not used

Tag_Select

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x20

Hard_Wired_Switch

Reserved

OOP

Ref_Sel_Mode

Revertive

HO_Usage

Internal Test

Phase_ Align

STC5423 Datasheet(PDF) 39 Page - Connor-Winfield Corporation

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