CC3200MODR1M2AMOBT datasheet(47/66 Pages) TI

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CC3200MOD

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SWRS166 – DECEMBER 2014

5.8.1.1

SRAM

The CC3200 family provides up to 256KB of zero-wait-state, on-chip SRAM. Internal RAM is capable of

selective retention during LPDS mode. This internal SRAM is located at offset 0x2000 0000 of the device

memory map.

Use the µDMA controller to transfer data to and from the SRAM.

When the device enters low-power mode, the application developer can choose to retain a section of

memory based on need. Retaining the memory during low-power mode provides a faster wakeup. The

application developer can choose the amount of memory to retain in multiples of 64KB. For more

information, see the API guide.

5.8.1.2

ROM

The internal zero-wait-state ROM of the CC3200 device is at address 0x0000 0000 of the device memory

and programmed with the following components:

•

Bootloader

•

Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces

The bootloader is used as an initial program loader (when the serial flash memory is empty). The CC3200

DriverLib software library controls on-chip peripherals with a bootloader capability. The library performs

peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support.

The DriverLib APIs in ROM can be called by applications to reduce flash memory requirements and free

the flash memory to be used for other purposes.

5.8.1.3

Memory Map

Table 5-5 describes the various MCU peripherals and how they are mapped to the processor memory. For

more information on peripherals, see the API document.

Table 5-5. Memory Map

START ADDRESS

END ADDRESS

DESCRIPTION

COMMENT

0x0000 0000

0x0007 FFFF

On-chip ROM (Bootloader + DriverLib)

0x2000 0000

0x2003 FFFF

Bit-banded on-chip SRAM

0x2200 0000

0x23FF FFFF

Bit-band alias of 0x2000 0000 through 0x200F FFFF

0x4000 0000

0x4000 0FFF

Watchdog timer A0

0x4000 4000

0x4000 4FFF

GPIO port A0

0x4000 5000

0x4000 5FFF

GPIO port A1

0x4000 6000

0x4000 6FFF

GPIO port A2

0x4000 7000

0x4000 7FFF

GPIO port A3

0x4000 C000

0x4000 CFFF

UART A0

0x4000 D000

0x4000 DFFF

UART A1

0x4002 0000

0x400 07FF

I2C A0 (Master)

0x4002 0800

0x4002 0FFF

I2C A0 (Slave)

0x4003 0000

0x4003 0FFF

General-purpose timer A0

0x4003 1000

0x4003 1FFF

General-purpose timer A1

0x4003 2000

0x4003 2FFF

General-purpose timer A2

0x4003 3000

0x4003 3FFF

General-purpose timer A3

0x400F 7000

0x400F 7FFF

Configuration registers

0x400F E000

0x400F EFFF

System control

0x400F F000

0x400F FFFF

µDMA

0x4200 0000

0x43FF FFFF

Bit band alias of 0x4000.0000 through 0x400F.FFFF

0x4401 C000

0x4401 EFFF

McASP

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