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ISL1591IRTZ Datasheet(PDF) 16 Page - Intersil Corporation

Part # ISL1591IRTZ
Description  Fixed Gain, Dual Port, VDSL2 Line Driver
PDF  18 Pages
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL1591IRTZ Datasheet(HTML) 16 Page - Intersil Corporation

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ISL1591
16
FN7625.1
October 31, 2012
Power Control Function
C0AB and C1AB control the quiescent current for the port
constructed from amplifiers A and B. If both control lines are
unconnected externally, the internal 50k
Ω pull-up will switch the
differential pairs to divert the 100µA tail currents into the supply
turning off the amplifiers. Taking both control pins low will pass
both IBIAS lines on into scaling current sources. When C0 and C1
are low, the typical 14mA total quiescent current for a port is
shown in the “Electrical Specification” tables on page 4. Taking
C0 high (>2V) while leaving C1 low (<0.8V) will reduce the current
into a port to a typical 9.7mA. Taking C1 high, while leaving C0
low will reduce the current in a port to a typical 7.4mA supply
current. Table 2 summarizes the operation modes for ISL1591
for each port.
Performance Considerations
Driving Capacitive Loads
All closed loop op amps are susceptible to reduced phase margin
when driving capacitive loads. This shows up as peaking in the
frequency response that can, in extreme situations, lead to
oscillations. The ISL1591 is designed to operate successfully
with small capacitive loads such as layout parasitics. As the
parasitic capacitance increases, it is best consider a small
resistor in series with the output to isolate the phase margin
effects of the capacitor. Figure 23 on page 9 shows the effect of
capacitive load. With 22pF on each output, we see about 6dB
peaking. This will increase quickly at higher CLOADS.
Output Headroom Model
Driving high voltages into heavy loads will require a careful
consideration of the available output swing vs. load. Figure 51
shows a useful model for predicting the available output swing. If
the output is modeled as ideal NPN and PNP transistors, the
output swing limits can be described as no load headrooms (VP
and VN) and an equivalent impedance to the supplies (RP and
RN).
The no load headrooms can be found in the “Electrical
Specifications” table on page 5 as 24V - 22.4V = 1.6V giving 0.8V
to each supply.
The equivalent impedances for this model can be extracted from
the reduced swings shown in the specification table for the 100
Ω
load. Looking at the typical 100
Ω load swings, we see a +21.2V
swing. Solving for the two resistors in the Headroom model
shown in Figure 51 gives Equation 7:
For the differential configuration, Figure 52 shows the Headroom
model that can be used to predict the maximum available swing
for a given supply voltage and load resistor, RL.
For equal bipolar supplies, the available peak output swing will
be given by Equation 8:
For example, to worst case the design using +24V supplies with
±5% supply tolerance and a minimum expected load of 50
Ω, a
maximum VP can be calculated as shown in Equation 9:
TABLE 2. POWER MODES OF THE ISL1591
C1
C0
OPERATION
00
IS Full Power Mode
01
IS Medium Power Mode
10
IS Low Power Mode
1
1
Power-Down
CO
C1
+3.3V
+VCC IBIAS
+1.4V
IBIAS +VCC
+3.3V
+1V
50k
Ω
50k
Ω
C1
+3.3V
+VCC IBIAS
+1.4V
IBIAS +VCC
+3.3V
50k
Ω
50k
Ω
CO
50k
Ω
FIGURE 50. BIAS CONTROL CIRCUIT
FIGURE 51. HEADROOM MODEL
+
–
+
–
+VS
GND
RP
RN
RL
VP
VN
±VO
(EQ. 7)
Rp = 2.8Ω and Rn =2.8Ω
FIGURE 52. HEADROOM MODEL
-
+
-
+
RL
VP
+VS
GND
L
n
p
n
p
s
p
R
R
R
V
V
V
V
+
+
−
−
=
1
)
(
2
(EQ. 8)
peak
L
n
p
n
p
s
peak
V
R
R
R
V
V
V
V
1
.
19
50
8
.
2
8
.
2
1
)
6
.
1
8
.
22
(
1
)
(
=
Ω
Ω
+
Ω
+
−
=
+
+
−
−
=
(EQ. 9)



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