PIC16F872SLASHSP datasheet(77/160 Pages) MICROCHIP

77 / 160 page

Preliminary

DS30221A-page 77

PIC16F872

9.2.15

CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit, or repeated start/stop condition,

deasserts the SCL pin (SCL allowed to float high).

When the SCL pin is allowed to float high, the baud rate

generator (BRG) is suspended from counting until the

SCL pin is actually sampled high. When the SCL pin is

sampled high, the baud rate generator is reloaded with

the contents of SSPADD<6:0> and begins counting.

This ensures that the SCL high time will always be at

least one BRG rollover count in the event that the clock

is held low by an external device (Figure 9-18).

9.2.16

SLEEP OPERATION

While in SLEEP mode, the I2C module can receive

addresses or data, and when an address match or

complete byte transfer occurs, wake the processor from

sleep (if the SSP interrupt is enabled).

9.2.17

EFFECTS OF A RESET

A RESET disables the SSP module and terminates the

current transfer.

FIGURE 9-18: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE

SCL

SDA

BRG overflow,

Release SCL,

If SCL = 1 Load BRG with

SSPADD<6:0>, and start count

BRG overflow occurs,

Release SCL, Slave device holds SCL low.

SCL = 1 BRG starts counting

clock high interval.

SCL line sampled once every machine cycle (TOSC

• 4).

Hold off BRG until SCL is sampled high.

TBRG

to measure high time interval

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