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PIC16F872/SP Datasheet(PDF) 17 Page - Microchip Technology |
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PIC16F872/SP Datasheet(HTML) 17 Page - Microchip Technology |
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17 / 160 page ![]() © 1999 Microchip Technology Inc. Preliminary DS30221A-page 17 PIC16F872 2.2.2.6 PIE2 REGISTER The PIE2 register contains the individual enable bits for the SSP bus collision interrupt and the EEPROM write operation interrupt. REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh) U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 —— — EEIE BCLIE — — — R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n= Value at POR reset bit7 bit0 bit 7: Unimplemented: Read as '0' bit 6: Reserved: Always maintain this bit clear bit 5: Unimplemented: Read as '0' bit 4: EEIE: EEPROM Write Operation Interrupt Enable 1 = Enable EE Write Interrupt 0 = Disable EE Write Interrupt bit 3: BCLIE: Bus Collision Interrupt Enable 1 = Enable Bus Collision Interrupt 0 = Disable Bus Collision Interrupt bit 2-1: Unimplemented: Read as '0' bit 0: Reserved: Always maintain this bit clear |
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