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PIC17C752-08/P Datasheet(PDF) 239 Page - Microchip Technology |
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PIC17C752-08/P Datasheet(HTML) 239 Page - Microchip Technology |
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239 / 320 page ![]() © 1997 Microchip Technology Inc. Preliminary DS30264A-page 239 PIC17C75X FIGURE 20-11: SPI SLAVE MODE TIMING (CKE = 0) TABLE 20-11: SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0) Param. No. Sym Characteristic Min Typ† Max Units Conditions 70 TssL2scH, TssL2scL SS ↓ to SCK↓ or SCK↑ input TCY *— — ns 71 TscH SCK input high time (slave mode) TCY + 20 * — — ns 72 TscL SCK input low time (slave mode) TCY + 20 * — — ns 73 TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 100 * — — ns 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 100 * — — ns 75 TdoR SDO data output rise time — 10 25 * ns 76 TdoF SDO data output fall time — 10 25 * ns 77 TssH2doZ SS ↑ to SDO output hi-impedance 10 * — 50 * ns 78 TscR SCK output rise time (master mode) — 10 25 * ns 79 TscF SCK output fall time (master mode) — 10 25 * ns 80 TscH2doV, TscL2doV SDO data output valid after SCK edge — — 50 * ns 83 TscH2ssH, TscL2ssH SS ↑ after SCK edge 1.5TCY + 40 * —— ns * Characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. SS SCK (CKP = 0) SCK (CKP = 1) SDO SDI 70 71 72 73 74 75, 76 77 78 79 80 79 78 SDI MSB LSB BIT6 - - - - - -1 MSB IN BIT6 - - - -1 LSB IN 83 Refer to Figure 20-1 for load conditions. |
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