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PIC17C752-08/P Datasheet(PDF) 243 Page - Microchip Technology |
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PIC17C752-08/P Datasheet(HTML) 243 Page - Microchip Technology |
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243 / 320 page  © 1997 Microchip Technology Inc. Preliminary DS30264A-page 243 PIC17C75X TABLE 20-14: I2C BUS DATA REQUIREMENTS Param. No. Sym Characteristic Min Max Units Conditions 100 THIGH Clock high time 100 kHz mode 2(TOSC)(BRG + 1) § — µs 400 kHz mode 2(TOSC)(BRG + 1) § — µs 1 MHz mode (1) 2(TOSC)(BRG + 1) § — µs 101 TLOW Clock low time 100 kHz mode 2(TOSC)(BRG + 1) § — µs 400 kHz mode 2(TOSC)(BRG + 1) § — µs 1 MHz mode (1) 2(TOSC)(BRG + 1) § — µs 102 TR SDA and SCL rise time 100 kHz mode — 1000 * ns Cb is specified to be from 10 to 400 pF 400 kHz mode 20 + 0.1Cb * 300 * ns 1 MHz mode (1) — 300 * ns 103 TF SDA and SCL fall time 100 kHz mode — 300 * ns Cb is specified to be from 10 to 400 pF 400 kHz mode 20 + 0.1Cb * 300 * ns 1 MHz mode (1) — 100 * ns 90 TSU:STA START condition setup time 100 kHz mode 2(TOSC)(BRG + 1) § — µs Only relevant for repeated START condition 400 kHz mode 2(TOSC)(BRG + 1) § — µs 1 MHz mode (1) 2(TOSC)(BRG + 1) § — µs 91 THD:STA START condition hold time 100 kHz mode 2(TOSC)(BRG + 1) § — µs After this period the first clock pulse is generated 400 kHz mode 2(TOSC)(BRG + 1) § — µs 1 MHz mode (1) 2(TOSC)(BRG + 1) § — µs 106 THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 * µs 1 MHz mode (1) TBD * — ns 107 TSU:DAT Data input setup time 100 kHz mode 250 * — ns Note 2 400 kHz mode 100 * — ns 1 MHz mode (1) TBD * — ns 92 TSU:STO STOP condition setup time 100 kHz mode 2(TOSC)(BRG + 1) § — µs 400 kHz mode 2(TOSC)(BRG + 1) § — µs 1 MHz mode (1) 2(TOSC)(BRG + 1) § — µs 109 TAA Output valid from clock 100 kHz mode — 3500 * ns 400 kHz mode — 1000 * ns 1 MHz mode (1) —— ns 110 TBUF Bus free time 100 kHz mode 4.7 ‡ — µs Time the bus must be free before a new transmission can start 400 kHz mode 1.3 ‡ — µs 1 MHz mode (1) TBD * — µs D102 ‡ Cb Bus capacitive loading — 400 * pF * Characterized but not tested. § This specification ensured by design. For the value required by the I2C specification, please refer to Figure E-11. ‡ These parameters are for design guidance only and are not tested, nor characterized. Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the parameter # 107 ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. Parameter # 102.+ # 107 = 1000 + 250 = 1250 ns (for 100 kHz-mode) before the SCL line is released. |
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