PIC17C752-08SLASHP datasheet(246/320 Pages) MICROCHIP

246 / 320 page

PIC17C75X

DS30264A-page 246

Preliminary

FIGURE 20-17: A/D CONVERSION TIMING

TABLE 20-18: A/D CONVERSION REQUIREMENTS

Param.

No.

Sym Characteristic

Min

Typ†

Max Units

Conditions

130

TAD

A/D clock period

PIC17CXXX

1.6

—

µs

TOSC based, VREF

≥ 3.0V

PIC17LCXXX

3.0

—

µsTOSC based, VREF full range

PIC17CXXX

2.0 *

4.0

6.0 *

µs

A/D RC Mode

PIC17LCXXX

3.0 *

6.0

9.0 *

µs

A/D RC Mode

131

TCNV

Conversion time

(not including acquisition time) (Note 1)

12 §

—

13 §

TAD

132

TACQ

Acquisition time

(Note 2)

10 *

—

µs

The minimum time is the

ampliﬁer settling time. This

may be used if the “new”

input voltage has not

changed by more than 1LSb

(i.e. 5mV @ 5.12V) from the

last sampled voltage (as

stated on CHOLD).

134

TGO

Q4 to ADCLK start

—

Tosc/2 §

—

If the A/D clock source is

selected as RC, a time of

TCY is added before the A/D

clock starts. This allows the

sleep instruction to be exe-

cuted.

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25

°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

This speciﬁcation ensured by design.

Note 1:

ADRES register may be read on the following TCY cycle.

See Section 16.1 for minimum conditions when input voltage has changed more then 1 LSb.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(TOSC/2) (1)

Note 1:

If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP

instruction to be executed.

1 TCY

. . .

PIC17C752-08/P Datasheet(PDF) 246 Page - Microchip Technology

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