PIC17C752-08SLASHP datasheet(125/320 Pages) MICROCHIP

125 / 320 page

Preliminary

DS30264A-page 125

PIC17C75X

FIGURE 15-5: SSPCON1: SYNC SERIAL PORT CONTROL REGISTER1 (ADDRESS 11h, BANK 6)

R/W-0

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7

bit0

bit 7:

WCOL: Write Collision Detect bit

Master Mode:

1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a

transmission to be started

0 = No collision

Slave Mode:

1 = The SSPBUF register is written while it is still transmitting the previous word

(must be cleared in software)

0 = No collision

bit 6:

SSPOV: Receive Overﬂow Indicator bit

In SPI mode

1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over-

ﬂow, the data in SSPSR is lost. Overﬂow can only occur in slave mode. The user must read the

SSPBUF, even if only transmitting data, to avoid setting overﬂow. In master mode the overﬂow bit is

not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.

0 = No overﬂow

In I2C mode

1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t

care" in transmit mode. SSPOV must be cleared in software in either mode.

0 = No overﬂow

bit 5:

SSPEN: Synchronous Serial Port Enable bit

In SPI mode

1 = Enables serial port and conﬁgures SCK, SDO, and SDI as serial port pins

0 = Disables serial port and conﬁgures these pins as I/O port pins

In I2C mode

1 = Enables the serial port and conﬁgures the SDA and SCL pins as serial port pins

0 = Disables serial port and conﬁgures these pins as I/O port pins

Note: In both modes, when enabled, these pins must be properly conﬁgured as input or output.

bit 4:

CKP: Clock Polarity Select bit

In SPI mode

1 = Idle state for clock is a high level

0 = Idle state for clock is a low level

In I2C slave mode

SCK release control

1 = Enable clock

0 = Holds clock low (clock stretch) (Used to ensure data setup time)

In I2C master mode

Unused in this mode

bit 3-0:

SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000

= SPI master mode, clock = FOSC/4

0001

= SPI master mode, clock = FOSC/16

0010

= SPI master mode, clock = FOSC/64

0011

= SPI master mode, clock = TMR2 output/2

0100

= SPI slave mode, clock = SCK pin. SS pin control enabled.

0101

= SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin

0110

= I2C slave mode, 7-bit address

0111

= I2C slave mode, 10-bit address

1000

= I2C master mode, clock = FOSC / (4 * (SSPADD+1) )

1xx1

= Reserved

1x1x

= Reserved

PIC17C752-08/P Datasheet(PDF) 125 Page - Microchip Technology

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