PIC17C752-08SLASHP datasheet(141/320 Pages) MICROCHIP

141 / 320 page

Preliminary

DS30264A-page 141

PIC17C75X

15.2.3

MASTER MODE

Master mode of operation is supported by interrupt

generation on the detection of the START and STOP

conditions. The STOP (P) and START (S) bits are

cleared from a reset or when the SSP module is dis-

abled. Control of the I2C bus may be taken when the P

bit is set, or the bus is idle with both the S and P bits

clear.

In master mode, the SCL and SDA lines are manipu-

lated by the SSP hardware.

The following events will cause SSP Interrupt Flag bit,

SSPIF, to be set (SSP Interrupt if enabled):

• START condition

• STOP condition

• Data transfer byte transmitted/received

FIGURE 15-20: SSP BLOCK DIAGRAM (I2C MASTER MODE)

Read

Write

SSPSR

Start bit, Stop bit,

Start bit detect,

SSPBUF

Internal

data bus

Set/Reset, S, P, WCOL (SSPSTAT)

shift

clock

MSb

LSb

SDA

Acknowledge

Generate

Stop bit detect

Write collision detect

Clock Arbitration

State counter for

end of XMIT/RCV

SCL

SCL in

Bus Collision

SDA in

SSPADD<6:0>

Baud

Set SSPIF, BCLIF

Reset ACKSTAT, PEN (SSPCON2)

rate

generator

SSPM3:SSPM0

PIC17C752-08/P Datasheet(PDF) 141 Page - Microchip Technology

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