PIC17C752-08SLASHP datasheet(143/320 Pages) MICROCHIP

143 / 320 page

Preliminary

DS30264A-page 143

PIC17C75X

The SSP Module shifts in the ACK bit from the

slave device, and writes its value into the

SSPCON2 register ( SSPCON2<6>).

10. The module generates an interrupt at the end of

the ninth clock cycle by setting SSPIF.

11. The user generates a STOP condition by setting

the STOP enable bit PEN in SSPCON2.

15.2.6

BAUD RATE GENERATOR

In I2C master mode, the reload value for the BRG is

located in the lower 7 bits of the SSPADD register

(Figure 15-21).

When the BRG is loaded with this

value, the BRG counts down to 0 and stops until

another reload has taken place. In I2C master mode,

the BRG is not reloaded automatically. If Clock Arbi-

tration is taking place for instance, the BRG will be

reloaded

when

the

SCL

sampled

high

(Figure 15-22).

FIGURE 15-21: BAUD RATE GENERATOR BLOCK DIAGRAM

FIGURE 15-22: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SSPM3:SSPM0

BRG Down Counter

CLKOUT

Fosc/4

SSPADD<6:0>

SSPM3:SSPM0

SCL

Reload

Control

Reload

SDA

SCL

SCL deasserted but slave holds

DX-1

BRG

SCL is sampled high, reload takes

place, and BRG starts its count.

03h

02h

01h

00h

03h

02h

reload

BRG

value

SCL low (clock arbitration)

SCL allowed to transition high

BRG counts

down

BRG counts

down

BRG counts

down

01h

00h

Note:There are two baud rate overﬂows per clock period. Clock period may be of variable time due to clock arbitration.

00h

PIC17C752-08/P Datasheet(PDF) 143 Page - Microchip Technology

PIC17C752-08/P Datasheet(HTML) 143 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL