PIC17C752-08SLASHP datasheet(152/320 Pages) MICROCHIP

152 / 320 page

PIC17C75X

DS30264A-page 152

Preliminary

15.2.10 I2C MASTER MODE RECEPTION

Master mode reception is enabled by programming

the receive enable bit, RCEN (SSPCON2<3>).

The baud rate generator begins counting, and

each rollover, the state of the SCL pin changes (high

to low/low to high), and data is shifted into the SSPSR.

After the falling edge of the eighth clock, the receive

enable ﬂag is automatically cleared, the contents of

the SSPSR are loaded into the SSPBUF, the BF ﬂag is

set, the SSPIF is set, and the baud rate generator is

suspended from counting, holding SCL low. The SSP

is now in IDLE state, awaiting the next command.

When the buffer is read by the CPU, the BF ﬂag is

automatically cleared. The user can then send an

acknowledge bit at the end of reception, by setting the

acknowledge

sequence

enable

bit,

ACKEN

(SSPCON2<4>).

Note: The SSP Module must be in IDLE mode

before the RCE bit is set, or the RCEN bit

will be disreguarded.

15.2.10.1 BF STATUS FLAG

In receive operation, BF is set when an address or

data byte is loaded into SSPBUF from SSPSR. It is

cleared when SSPBUF is read.

15.2.10.2 SSPOV STATUS FLAG

In receive operation, SSPOV is set when 8 bits are

received into the SSPSR, and the BF ﬂag is already

set from a previous reception.

15.2.10.3 WCOL STATUS FLAG

If the user writes the SSPBUF when a receive is

already in progress (i.e. SSPSR is still shifting in a

data byte), then WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

PIC17C752-08/P Datasheet(PDF) 152 Page - Microchip Technology