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PIC17C752-08/P Datasheet(PDF) 159 Page - Microchip Technology |
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PIC17C752-08/P Datasheet(HTML) 159 Page - Microchip Technology |
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159 / 320 page ![]() © 1997 Microchip Technology Inc. Preliminary DS30264A-page 159 PIC17C75X 15.2.13 CLOCK ARBITRATION Clock arbitration occurs when the master during any receive, transmit, or restart/stop condition de-asserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the baud rate genera- tor (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device. (Figure 15-36) FIGURE 15-36: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE SCL SDA BRG overflow, Release SCL, If SCL = 1 Load BRG with SSPADD<6:0>, and start count BRG overflow occurs, Release SCL, Slave device holds SCL low. SCL = 1 BRG starts counting clock high interval. SCL line sampled once every machine cycle (Tosc • 4). Hold off BRG until SCL is sampled high. T BRG T BRG T BRG to measure high time interval |
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