LM5085SDESLASHNOPB datasheet(20/33 Pages) TI

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R4 =

25 mV

IOR(min)

CIN + CBYP =

IOUT(max) x tON(max)

= 25.5 PF

5A x 2.55 Ps

0.5V

LM5085, LM5085-Q1

SNVS565I – NOVEMBER 2008 – REVISED AUGUST 2015

www.ti.com

Typical Application (continued)

CIN, CBYP:These capacitors limit the voltage ripple at VIN by supplying most of the switch current during the on-

time. At maximum load current, when Q1 is switched on, the current through Q1 suddenly increases to the lower

peak of the inductor’s ripple current, then ramps up to the upper peak, and then drops to zero at turn-off. The

average current during the on-time is the load current. For a worst case calculation, these capacitors must supply

this average load current during the maximum on-time, while limiting the voltage drop at VIN. For this example,

0.5V is selected as the maximum allowable droop at VIN. The minimum input capacitance is calculated from:

(29)

A 33µF electrolytic capacitor is selected for CIN, and a 1µF ceramic capacitor is selected for CBYP. Due to the

ESR of CIN, the ripple at VIN will likely be higher than the calculation indicates, and therefore it may be desirable

to increase CIN to 47µF or 68µF. CBYP must be located as close as possible to the VIN and GND pins of the

LM5085. The voltage rating for both capacitors must be at least 55V. The RMS ripple current rating for the input

capacitors must also be considered. A good approximation for the required ripple current rating is IRMS > IOUT/2.

D1: A Schottky diode is recommended. Ultra-fast recovery diodes are not recommended as the high speed

transitions at the SW node may affect the regulator’s operation due to the diode’s reverse recovery transients.

The diode must be rated for the maximum input voltage, and the worst case current limit level. The average

power dissipation in the diode is calculated from:

PD1 = VF x IOUT x (1-D)

(30)

where VF is the diode’s forward voltage drop, and D is the on-time duty cycle. Using Equation 1, the minimum

duty cycle occurs at maximum input voltage, and is calculated to be

≊9.1% in this example. The diode power

dissipation calculates to be:

PD1 = 0.65V x 5A x (1- 0.091) = 2.95W

(31)

CVCC: The capacitor at the VCC pin (from VIN to VCC) provides not only noise filtering and stability for the VCC

regulator, but also provides the surge current for the PFET gate drive. The typical recommended value for CVCC

is 0.47µF. A good quality, low ESR, ceramic capacitor is recommended. CVCC must be located as close as

possible to the VIN and VCC pins. If the selected PFET has a Total Gate Charge specification of 100nC or

larger, or if the circuit is required to operate at input voltages below 7V, a larger capacitor may be required. The

maximum recommended value for CVCC is 1µF.

IC Power Dissipation: The maximum power dissipated in the LM5085 package is calculated using Equation 14

at the maximum input voltage. The Total Gate Charge for the Si7465 PFET is specified to be 40nC (max) in its

data sheet. Therefore the total power dissipation within the LM5085 is calculated to be:

PDISS = 55V x ((40nC x 300kHz) + 1.4mA) = 737mW

(32)

Using an HVSSOP package with a

θJA of 46°C/W produces a temperature rise of 34°C from junction to ambient.

8.2.2.2 Alternate Output Ripple Configurations

The minimum ripple configuration employing C1, C2, and R3 in Figure 25 results in a low ripple amplitude at

VOUT determined mainly by the characteristics of the output capacitor and the ripple current in L1. This

configuration allows multiple ceramic capacitors to be used for VOUT if the output voltage is provided to several

places on the PC board. However, if a slightly higher level of ripple at VOUT is acceptable in the application, and

distributed capacitance is not used, the ripple required for the FB comparator pin can be generated with fewer

external components using the circuits shown below.

a) Reduced ripple configuration: In Figure 27, R3, C1 and C2 are removed (compared to Figure 25). A low

value resistor (R4) is added in series with COUT, and a capacitor (Cff) is added across RFB2. Ripple is generated

at VOUT by the inductor ripple current flowing through R4, and that ripple voltage is passed to the FB pin via Cff.

The ripple at VOUT can be set as low as 25 mVp-p since it is not attenuated by RFB2 and RFB1. The minimum

value for R4 is calculated from:

(33)

where IOR(min) is the minimum ripple current, which occurs at minimum input voltage. The minimum value for Cff

is determined from:

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