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LM5085SDE/NOPB Datasheet(PDF) 23 Page - Texas Instruments

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Part # LM5085SDE/NOPB
Description  75V Constant On-Time PFET Buck Switching Controller
PDF  33 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

LM5085SDE/NOPB Datasheet(HTML) 23 Page - Texas Instruments

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1
2
3
4
5
8
7
6
Exposed Pad on Bottom
Connect to Ground
FB
PGATE
ISEN
GND
VCC
ADJ
RT
VIN
RSEN
RT and ADJ
Connections
(Tap to CIN)
CIN
CVCC
L1
COUT
D1
VIN
GND
RFB1
Keep
CIN, D1, Q1
Loop Small
Q1
VOUT
LM5085, LM5085-Q1
www.ti.com
SNVS565I – NOVEMBER 2008 – REVISED AUGUST 2015
9 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 4.5 V and 75 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the device, additional
bulk capacitance may be required at the input terminals of the converter in addition to the calculated values to
limit the inductive spikes due to the input cables or wires.
10 Layout
10.1 Layout Guidelines
In most applications, the heat sink pad or tab of Q1 is connected to the switch node, i.e. the junction of Q1, L1
and D1. While it is common to extend the PC board pad from under these devices to aid in heat dissipation, the
pad size should be limited to minimize EMI radiation from this switching node. If the PC board layout allows, a
similarly sized copper pad can be placed on the underside of the PC board, and connected with as many vias as
possible to aid in heat dissipation.
The voltage regulation, over-voltage, and current limit comparators are very fast and can respond to short
duration noise pulses. Layout considerations are therefore critical for optimum performance. The layout must be
as neat and compact as possible with all the components as close as possible to their associated pins. Two
major current loops conduct currents which switch very fast, requiring the loops to be as small as possible to
minimize conducted and radiated EMI. The first loop is that formed by CIN, Q1, L1, COUT, and back to CIN. The
second loop is that formed by D1, L1, COUT, and back to D1. The connection from the anode of D1 to the ground
end of CIN must be short and direct. CIN must be as close as possible to the VIN and GND pins, and CVCC must
be as close as possible to the VIN and VCC pins.
If the anticipated internal power dissipation of the LM5085 will produce excessive junction temperatures during
normal operation, a package option with an exposed pad must be used (HVSSOP-8 or WSON-8). Effective use
of the PC board ground plane can help dissipate heat. Additionally, the use of wide PC board traces, where
possible, helps conduct heat away from the IC. Judicious positioning of the PC board within the end product,
along with the use of any available air flow (forced or natural convection) also helps reduce the junction
temperature.
10.2 Layout Example
Figure 33. LM5085 Buck Converter Layout Example
Copyright © 2008–2015, Texas Instruments Incorporated
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Product Folder Links: LM5085 LM5085-Q1



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