AR0230CSSC00SUEA0-DRBR datasheet(18/36 Pages) ONSEMI

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AR0230CS/D Rev. 8, Pub. 11/15 EN

©Semiconductor Components Industries, LLC, 2015.

AR0230CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor

Features Overview

Adaptive Color Difference (ADACD) Noise Filtering

A good noise reduction filter will remove noise from an image while retaining as much

image detail as possible. To retain image detail, the noise reduction filter must adapt to

the image signal. To remove noise, the noise reduction filter must adapt to the noise level

of the image signal. The key is to remove the appropriate amount of noise. Over-filtering

will cause image blurring while under-filtering will leave noise in the image. The AdaCD

algorithm relies on a noise model derived from characterization data to aid in separating

noise from signal.

The AR0230CS AdaCD algorithm performs pixel-by-pixel color noise correction for each

of the red, blue, and green color planes. Each pixel is corrected based on surrounding

pixel values on the same color plane and a noise model. The noise model is based on

characterization data, and takes into account applied analog gain.

Fast Mode Switch (Combi Mode)

To facilitate faster switching between linear and HDR modes, the AR0230CS includes a

Combi Mode feature. When enabled, Combi Mode loads a single (HDR) sequencer.

When switching from HDR to linear modes, the sequencer remains the same, but only

the T1 image is output. While not optimized for linear mode operation, it allows faster

mode switching as a new sequencer load is not needed. Switching between modes may

result in the output of one bad frame.

Analog/Digital Gains

A programmable analog gain of 1.5x to 12x (HDR) and 1.5x to 16x (linear) applied simul-

taneously to all color channels will be featured along with a digital gain of 1x to 16x that

may be configured on a per color channel basis.

Skipping/Binning Modes

The AR0230CS supports subsampling. Subsampling allows the sensor to read out a

smaller set of active pixels by either skipping, binning, or summing pixels within the

readout window. Horizontal binning is achieved in the digital readout. The sensor will

sample the combined 2x adjacent pixels within the same color plane. Vertical row

binning is applied in the pixel readout. Row binning can be configured as 2x rows within

the same color plane. Pixel skipping can be configured up to 2x in both the x-direction

and y-direction. Skipping pixels in the x-direction will not reduce the row time. Skipping

pixels in the y direction will reduce the number of rows from the sensor effectively

reducing the frame time. Skipping will introduce image artifacts from aliasing.

The AR0230CS supports row wise vertical binning. Row wise vertical summing is not

supported.

Clocking Options

The sensor contains a phase-locked loop (PLL) that is used for timing generation and

control. The required VCO clock frequency is attained through the use of a pre-PLL clock

divider followed by a multiplier. The PLL multiplier should be an even integer. If an odd

integer (M) is programmed, the PLL will default to the lower (M-1) value to maintain an

even multiplier value. The multiplier is followed by a set of dividers used to generate the

output clocks required for the sensor array, the pixel analog and digital readout paths,

and the output parallel and serial interfaces. Use of the PLL is required when using the

HiSPi interface.

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