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AR0230CSSC00SUEA0-DRBR Datasheet(PDF) 33 Page - ON Semiconductor |
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AR0230CSSC00SUEA0-DRBR Datasheet(HTML) 33 Page - ON Semiconductor |
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33 / 36 page ![]() AR0230CS/D Rev. 8, Pub. 11/15 EN 33 ©Semiconductor Components Industries, LLC, 2015. AR0230CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor Power-On Reset and Standby Timing Power-Down Sequence The recommended power-down sequence for the AR0230CS is shown in Figure 12. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Disable streaming if output is active by setting standby R0x301a[2] = 0 2. The soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. Turn off VDD_SLVS. 4. Turn off VDD. 5. Turn off VDD_IO. 6. Turn off VAA/VAA_PIX. 7. Turn off VDD_PLL. Figure 12: Power Down t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged. Table 21: Power-Down Sequence Definition Symbol Minimum Typical Maximum Unit VDD_SLVS to VDD t0 0 – – s VDD to VDD_IO t1 0 – – s VDD_IO to VAA/VAA_PIX t2 0 – – s VAA/VAA_PIX to VDD_PLL t3 0 – – s Power Down until Next Power Up Time t4 100 – – ms V DD_IO (1.8/2.8) t4 t 0 t1 t3 t2 EXTCLK VDD_SLVS (0.4) VDD (1.8) VAA_PIX VAA (2.8) VDD_PLL (2.8) Power Down until next Power up cycle |
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