UVLO

LM5032

1.25V

20 2A

Max. Duty

Cycle Limiter

R1A

R1B

R2

Z1

PWM

Controller #1

Softstart

#1

COMP1

SS1

Shutdown

Control

PWM

Controller # 2

COMP2

To Output

Drivers

Softstart

# 2

SS2

Coupler

Opto -

Coupler

Opto -

LM5032

LM5032

www.ti.com

SNVS344B – MARCH 2005 – REVISED DECEMBER 2014

Application Information (continued)

Figure 27. Shutting Down One Regulator Channel

8.1.10 Line Voltage Dependent Maximum Duty Cycle

the graph of Figure 9. Using values from the example above (R1 = 150 k

Ω, R2 = 10 kΩ in Figure 22), the

maximum duty cycle varies as shown in Figure 10. If it is desired to increase the slope of the ramp in Figure 10,

Figure 28 shows a suggested configuration. After the LM5032 is enabled, Z1 clamps the voltage across R1B,

8.1.11 User Defined Max Duty Cycle

The maximum allowed duty cycle at OUT1 and OUT2 can be set with a resistor from DCL to GND1. See

Figure 8 and Equation 2. The default maximum duty cycle (80%) determined by the internal clock signals can be

selected. The DCL pin should not be left open.

8.2 Typical Application

Figure 29 shows an example of an LM5032-controlled 200-W interleaved regulator which provides a single

regulated 48-V output. The interleaving of two power stages to a single output reduces the ripple voltage across

both input and output capacitors, and improves the power stage efficiency compared to a single-stage design.

Since the two interleaved control blocks are used to regulate a single combined output, the two soft-start pins

SS1 and SS2 are connected to a single soft-start capacitor, and the two COMP1 and COMP2 pins are

connected together to a single error amplifier.

Copyright © 2005–2014, Texas Instruments Incorporated

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