40k

100k

R1

R2

R3

C1

PWM

COMP

CV

No Lead

Network

Required

ERROR

AMP

FB

TRK/SS

0.75V

CS

Current

Sense Amp

1.27V

Negative Current

Comparator

1V

Low Side

Enable

Vbias

2.35V

ILIMIT SLOW

Gm = 5 mA/V

2V

ILIMIT FAST

CO

AV=16

FB

TRK/SS

CV

PWM

Comparator

CRMIX

to PWM

Latch

ERROR

AMP

0.75V

COMP

LM5115A

SNVS467B – DECEMBER 2006 – REVISED MARCH 2013

www.ti.com

The capacitor C1 is connected in series with R3 to increase the dc gain of the voltage regulation loop and

improve output voltage accuracy. The corner frequency set by R3 x C1 should be less than 1/10th of the cross-

over frequency of the overall converter such that capacitor C1 does not add phase lag at the crossover

frequency.

Figure 21. Current Sensing and Limiting

Figure 22. Voltage Sensing and Feedback

Current Limiting (CS, CO and VOUT)

Current limiting is implemented through the current sense amplifier as illustrated in Figure 21. The current sense

amplifier monitors the inductor current that flows through a sense resistor connected between CS and VOUT.

The voltage gain of the current sense amplifier is nominally equal to 16. The output of current sense signal is

shifted by 1.27V to produce the internal CV reference signal. The CV signal drives two current limit amplifiers.

Both of the current limit amplifiers have open drain (sink only) output stages which are connected to the CO pin.

The CO pin is typically connected to the COMP pin through a diode (the cathode is connected to the CO pin and

the anode is connected to the COMP pin). The slow current limit amplifier has a nominal transconductance of 5

mA/V and provides constant current mode operation at the desired current limit set point. The fast current limit

amplifier has nominal current pull-down capability of 100mA and provides protection against fast over-current

conditions. During normal operation, the voltage error amplifier controls the COMP pin voltage which adjusts the

16

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