ADP3430

http://onsemi.com

5

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Reference Current

Reference Bias Voltage

1.5

V

Reference Bias Current

14.25

15

15.75

mA

Error Amplifier

Output Voltage Range (Note 2)

0

4.4

V

Accuracy

Relative to nominal DAC output,

Referenced to FBRTN, LLINE = CSREF

−11.0

+11.0

mV

Load Line Positioning Accuracy

In startup CSREF − LLINE = 80 mV,

DAC = 1.51875 V

1.092

−82

1.1

−80

1.108

−78

V

mV

Differential Non−linearity

−1.0

+1.0

LSB

FBRTN Current

125

200

mA

Output Current

500

mA

Gain Bandwidth Product

COMP = FB

20

MHz

Slew Rate

COMP = FB

25

V/ms

LLINE Input Voltage Range

Relative to CSREF

−250

+250

mV

LLINE Input Bias Current

−10

+10

nA

BOOT Voltage Hold Time

1.0

ms

VID Inputs

Input Low Voltage

VID(X)

0.3

V

Input High Voltage

VID(X)

0.8

V

Input Current

−1.0

mA

VID Transition Delay Time (Note 2)

VID code change to FB change

400

ns

No CPU Detection Turn−Off Delay Time

(Note 2)

VID code change to PWM going low

5.0

ms

PSI Input

Input Low Voltage

0.3

V

Input High Voltage

0.8

V

Input Current

PSI = HIGH

1.0

mA

Assertion Time

150

ns

De−assertion Time

260

ns

TRDET Output

Low Voltage

150

300

mV

Oscillator

Frequency Range

0.25

4.0

MHz

Frequency Variation

270

300

500

800

330

kHz

Output Voltage

1.9

2.0

2.1

V

RAMP Output Voltage

RAMP − FB

−50

+50

mV

RAMP Input Current Range

1.0

200

mA

Current Sense Amplifier

Offset Voltage

CSSUM − CSREF, CSREF = 0.8V ~1.6V

−1.0

+1.0

mV

Input Bias Current

−10

+10

nA

Gain Bandwidth Product

CSSUM = CSCOMP

10

MHz

Slew Rate

10

V/ms

Input Common−Mode Range

CSSUM and CSREF

0

3.5

V

Output Voltage Range

0.05

3.5

V

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not tested in production.