| Electronic Components Datasheet Search |
|
ADP3430 Datasheet(PDF) 4 Page - ON Semiconductor |
|
|
|||||||||||||||||||||||||||||
ADP3430 Datasheet(HTML) 4 Page - ON Semiconductor |
|
4 / 26 page ![]() ADP3430 http://onsemi.com 4 PIN ASSIGNMENT Pin No. Mnemonic Description 1 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. 2 PWRGD Power−Good Output. Open−drain output that signals when the output voltage is outside of the proper operating range. 3 FBRTN Feedback Return. VID DAC and error amplifier input for remote sensing of the output voltage. 4 FB Feedback Input. Error amplifier reference for remote sensing of the output voltage. 5 COMP Error Amplifier Output and Compensation Point. 6 SS Soft−Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft−start ramp−up time. 7 DELAY Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent latchoff delay time, boot voltage hold time, EN delay time, and PWRGD delay time. 8 TRDET Transient Detection Output. This pin is pulled low when a load release transient is detected. 9 VRHOT VR Hot Output. Active high open−drain output that signals when the temperature of the temperature sensor connected to TTSNS exceeds the programmed VRHOT temperature threshold. 10 TTSNS VR Hot Thermal Throttling Sense Input. An NTC thermistor between this pin and GND is used to remotely sense the temperature at the desired thermal monitoring point. 11 ILIM Current Sense and Limit Pin. Connecting a resistor from this pin to CSCOMP sets the internal current sensing signal for current limit and IMON. 12 RT Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the PWM oscillator frequency. The switching frequency for each phase is up to 800 KHz. 13 RAMP PWM Ramp Slope Setting Input. An external resistor from the converter input voltage to this pin sets the slope of the internal PWM ramp. 14 LLINE Output Load Line Programming Input. This pin can be directly connected to CSCOMP, or it can be connected to the center point of a resistor divider between CSCOMP and CSREF. Connecting LLINE to CSREF disables positioning. 15 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the power−good and crowbar functions. This pin should be connected to the common point of the output inductors. 16 CSSUM Current Sense Summing Node. External resistors from each switch node to this pin sum the inductor currents together to measure the total output current. 17 CSCOMP Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of the current sense amplifier and the positioning loop response time. 18 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground. 19 OD Output Disable Logic Output for phase 1. This pin is actively pulled low when the EN input is low or when VCC is below its UVLO threshold to signal to the Driver IC that the driver high−side and low−side outputs should go low. This pin needs to connect to both 1st and 2nd phase gate drivers. 20 IREF Current Reference Input. An external resistor from this pin to ground sets the internal reference current used to generate IFB, IDELAY, ISS, ICL, and ITTSNS. 21 IMON IMON Total Current Output Pin. A resistor/capacitor from this pin to FBRTN/VSS Sense sets the IMON signal. 22 NC No Connection 23 to 25 SW3 to SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open. 26 ODN Output Disable Logic output for PSI Operation. This pin is pulled low when PSI is low, otherwise it functions the same as OD. This pin needs to connect to the 3rd phase gate driver. 27 NC No Connection 28 to 30 PWM3 to PMW1 Logic−Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3121. Connecting the PWM4, and/or PWM3 output to VCC causes that phase to turn off, allowing the ADP3430 to operate as a 2− or 3−phase controller. 31 VCC Supply Voltage for the Device. A 340W resistor should be placed between the 12 V system supply and the VCC pin. The internal shunt regulator maintains VCC = 5.0 V. 32 to 39 VID7 to VID0 Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a Logic 0 if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.5 V to 1.6 V. 40 PSI Power State Indicator Input. Pulling this pin low places controller in lower power state operation. PSI = Low demands 2−phase operation, PSI = High for 3−phase. While PSI is an input signal which supports OTF change. |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |