PDSP16515GCPR datasheet(12/27 Pages) MITEL

12 / 27 page

PDSP16515A

In the system illustrated by Figure 6, the host also controls the

mode of operation of the FFT processor. The DEF signal is

produced from an address decode, and the control

parameters are loaded from the host bus by connecting the

AUX inputs to the data outputs.

Real Only Transfprms With a Single Device

In the simplest case real transforms can, of course, be

computed by forcing zero levels on the imaginary input pins.

The device can, however, be configured to internally perform

two simultaneous real transforms instead of a single complex

transform. The block floating point logic will then use data from

both blocks when it determines the number of shifts to be

applied. This dual transform technique is used to increase the

maximum permissible sampling rates, but since an additional

data pass is required in order to un-scramble the transformed

data, the actual performance is not quite double that possible

with a complex transform of the same size. The 4 x 64 point

complex mode becomes an 8 x 64 real mode, but the change

from 16 x 16 complex transforms to 32 x 16 real transforms is

not supported.

When a real transform is performed the algorithm produces

complex results for each of the incoming data blocks, but each

result only represents the first half of the frequency domain

data. This does not cause any loss of information since the two

halves are mirror images of each other. As with complex

transforms, it is necessary for a different system configuration

to be used when 1024 point transforms are required. These

are considered later, and the following only applies to 256 or

64 point transforms.

In a single device system, performing non overlapped

transforms on data from a SINGLE source, only the Real input

pins are used, and the Imaginary inputs are redundant except

when configuring the device. By setting Control Register Bits

8:6 to 101, however, it is possible for a single device to accept

data from two independent sources using the real and

imaginary inputs. Maximum sampling rates will then only be

half those possible when a single source is used, if no

incoming data is to remain un-processed. With two sources a

transform must be completed in the time to load parallel

blocks, otherwise incoming data will be lost. With one source

a transform need not be finished until two data blocks have

been acquired. In this dual input mode results from data on the

real inputs always precede those from the imaginary inputs.

If block overlapping is needed, it is always necessary to load

pairs of data blocks simultaneously, using both the real and

imaginary inputs. With dual sources of data this presents no

problem, and Control Bits 8:6 should be set to 110 or 111 for

the relevant amount of overlapping. If data is from a single

source an external FIFO is needed to provide a simple delay

for a block of data. Decodes 001 through 100 from Control Bits

8:6 must be used to select the required overlap.

Valid transformed data is actually available within the device

from DAV going active until INEN again goes active, and a

new set of data is loaded. The output tristate drivers, however,

normally go high impedance when DAV goes in-active once a

dump operation has been completed. In order to support

systems in which it may be necessary to read the transformed

data more than once, a Control Register Bit is provided which

keeps the DAV output active until a further INEN edge is

received. The user must then keep track of how many outputs

have been dumped before INEN is generated to start a new

load operation.

The DAV output can be delayed by an amount equivalent to

the pipeline delay through the PDSP16330. This option is

invoked by setting a control bit, and allows DAV to indicate that

polar data is available at the output of the PDSP16330. When

the option is used the tri-state outputs will be enabled when

data is actually available and DEN is active, and not when DAV

eventually goes active.

Two Control Register Bits allow a range of dump size options

to be supported. In some applications the results of interest

may only lie in the lower 25 or 50% of the frequency bins, the

sampling rate having been chosen to prevent aliasing, and the

transform size having been selected to give the required

frequency resolution. In other systems it is only necessary to

output the second half of a given sized transform. This is useful

when filtering is to be performed in the frequency domain using

Overlap /Discard Fast Convolutions. With this method FIR

filters with N taps can be implemented in the frequency domain

using 50% overlapped transforms on 2N samples. After

multiplication in the frequency domain with the required

frequency response, the inverse transform is performed and

the first half of each output is discarded. Since only half the

results are dumped, the dump clock need not be twice the rate

of the clock used to load data.

Full Co- Processor Operation

A single device can be configured as a co-processor to a host

system in which both the loading and dumping of data is under

the control of the host. Such a system is shown in Figure 6, in

which DEN is a host provided enable for host read operations,

and INEN is an enable for host write operations. DIS and DOS

are host data strobes.

The host loads a block of data into the PDSP16515A, using

DIS enabled by INEN, which is then automatically

transformed. The DAV output provides a flag indicating that

the transform is complete, and results are then read by the

host using DOS enabled by DEN. A new set of inputs is not

normally loaded until the previous results are complete. If,

however, 1024 point transforms are not to be performed,

loading new data could coincide with dumping previous

results. This, however, would require a host system with

separate input and output buses, and which also allowed

coincident transfers. As discussed previously, transferring

results must take no longer than loading new data to prevent

corruption of the outputs.

PDSP16515GCPR Datasheet(PDF) 12 Page - Mitel Networks Corporation

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