PDSP16515GCPR datasheet(15/27 Pages) MITEL

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PDSP16515A

Without the feedback from the last device, the first device

would wait for another externally supplied initialising pulse. In

such a system with N devices in parallel, then N continuous

transforms must be executed before the first device can wait

for a new INEN input.

When only one output processor is provided the data outputs

from all devices are connected together, and internal logic will

enable the tri-state outputs when a device is ready to output

data i.e. DAV goes active. When data blocks are overlapped

it is possible that the output rate requirements will limit the

input sampling rate (see section on Multiple Device Sampling

Rates). Additional output processors will remove this

restriction, and the correct choice of multiple device operating

mode will optimise the sampling rates that can be achieved

with a given number of devices.

The synchronisation intervals, necessary to co-ordinate input

and output operations with the transform operation, lead, in

effect, to some uncertainty in the time needed to complete a

transform. Thus a particular device in a multiple device system

can effectively complete a transform in less system clock

periods than another device in the same system. To prevent

one device turning on its output bus before the previous one

has finished, it is either necessary to use a faster output rate

than would otherwise be required, or to use the inverted DAV

output from one device to drive the DEN input of the next. The

latter option allows DIS and DOS to be connected together,

and ensures that the second device will not output data until

the first device has finished.

This method of driving the DEN input from the inverted DAV

output from a previous device requires a change to the single

device DAV and DEN operation. If DEN is active at the end of

a transform in a multiple device system, the DAV output will go

active when the output circuit has been primed by the DOS

strobes. This operation is identical to that provided for a single

device system, and is transparent to the user as long as DEN

and DOS are active . If DEN is not active, however, the DAV

output will not asynchronously go active as happens in a single

device system. Instead DAV will only go active when DEN

eventually goes active. Since DEN is the inverted DAV output

from a previous device, it is thus never possible for two devices

to be actively outputtng data. The DAV active going edge

remains synchronised to the DOS strobe since the DEN input

will only go active when a previous DAV goes in-active. A

further change to the output circuitry ensures that the output

buffer is primed even though DEN is not active. The first word,

however, only progresses as far as the final output latch. The

output bus is not enabled, and address increments do not

occur, until DEN is finally received. This modification to the

internal control logic ensures that the output buffer does not

impose unnecessary gaps between consecutive transforms.

These gaps would, in turn, force the required DOS frequency

to be greater than the DIS frequency ( or greater than twice or

four times the frequency with 50% and 75% overlaps ).

The system illustrated by Figure 9 produces a common DAV

output by OR'ing together all the individual, active low, DAV

outputs. This is not guaranteed to give an indication when one

transform has finished, and the next one has started, since it

may simply glitch as one DAV goes in-active and the next one

goes active after some delay. This glitch will not cause system

problems since it occurs at a point clear of the high going edge

of the DOS strobe. To provide a marker for the end of a

transform each in-active going DAV edge should set its own

latch, which is then reset by a subsequent DOS edge. The

output of the latches can then be OR'd together if necessary.

Three multiple device operating modes are actually provided,

and are selected with Control Register Bits 10:9. The choice

of a particular mode is application dependent, and will effect

the maximum sampling rate achievable with a given number

of devices.

Multiple DEevice Sampling Rates

Mode 1. (BITS 10:9 = 01)

In this mode transfers in and out of the device are concurrent

with transform operations. This mode must not be used for

1024 point transforms due to internal memory size

restrictions. When real transforms are performed in this mode,

only the real data input is used, regardless of the amount of

block overlapping.

The increase in performance is directly related to the number

of devices provided, but the input and output rates are limited

to FØ where F and Ø are as defined previously. Within this

restriction the theoretical performance is given by;

NnS > PK+4W, or 0.5NnS > PK+4W, or 0.25NnS > PK+4W

for 0%, 50%, or 75% overlapping. N is the number of devices,

n is the transform size, S is the DIS strobe period, P is the

number of system clock periods given in Table 4, K is the

system clock period, and W is the DOS strobe period. Note

that DIS should be synchronous to SCLK, and also that DOS

should be synchronous to SCLK.

If an output processor is provided for every device, two

devices with 50% block overlapping or four devices with 75%

block overlapping will give the same sampling rates as a single

device with no overlapping. If only one output processor is

provided, the two or four times increase needed in the output

rate over the input rate, usually imposes a limit on the input

rate, since the output rate is limited to a factor, F, of SCLK.

PDSP16515GCPR Datasheet(PDF) 15 Page - Mitel Networks Corporation

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