PDSP16515GCPR datasheet(14/27 Pages) MITEL

14 / 27 page

PDSP16515A

Table 5 assume that a 40 MHz I/O rate is used, and that all

results are dumped.

Multiple Device Systems

In real time applications several devices may be used in

parallel in order to increase the sampling rate, but not to

increase the transform size. When all outputs are commoned

together, and feed a single output processor, then the data

dump time must always be less than or equal to the time taken

to load the data block ( or 50% or 25% of the time with block

overlapping ). In most configurations with block overlapping

the dump rate requirements will limit the maximum input rate,

if only one output processor is provided. This can be avoided

if the system provides separate output processors for every

device. The system clock used for internal calculations then

ultimately imposes a limit on the maximum sampling rate

possible.

A multiple device system performing complex transforms with

a single output processor is shown in Figure 7. The INEN/

LFLG signals are used to co-ordinate the segmentation of

data between devices. The in-active going edge of LFLG

instigates the load procedure in the next device, and, since this

edge can be programmed to occur either 25%, 50%, or 100%

through the load operation, it can cause the next device to

commence loading before the previous one has finished. In

this manner data block overlapping is achieved. When

multiple concurrent transforms are performed ( for example 4

x 64 or 8 x 64 ) two LFLG transitions are sometimes needed

to support block overlapping. This is fully explained in the

section on Mode 1 sampling rates.

In any of the multiple device modes an INEN edge transition

is needed to start a new load procedure when the previous one

has finished. When the LFLG output from the last device is fed

back to the INEN input of the first device, continuous

transforms will be executed. This continuous sequence can

be started by the rising edge of DEF if Control Register Bit 12

is set in the first device (see section on Loading Data). This bit

must not be set in the other devices. Since all devices are

supplied from a common input bus and have a common

source of control parameters, this Bit 12 inversion is best

mechanized with an Exclusive OR gate in the AUX12 input line

of the first device. The input can then be inverted when DEF

is active but otherwise not be effected. Once the first device

has been started with the DEF edge, the sequence will

continue automatically using the LFLG /INEN connection

between devices.

In many applications data is transformed continuously after

power on, and the concept of a first data sample does notexist.

If, however , the opposite is true, the first data sample must be

present on the input pins such that it can be loaded with the

second rising DIS edge after DEF has gone in-active. The data

must meet the set up and hold times given in Table 1, and DEF

itself must meet the parameters normally met by the INEN

rising edge. The latter requirement is necessary to avoid a

possible one DIS cycle variance, due the internal DEF

synchronization logic. If the position of the first data sample is

not important, it is not necessary for DEF to have any set up

specification.

The maximum sampling rates given in Table 5 allow for the

extra dumping time.

The load and dump operations are not concurrent with

transforms in the 1024 point modes, and an external input

buffer will be needed if loss of incoming data is to be avoided.

This is loaded at the sampling rate and then data is transferred

to the PDSP16515A at a user defined rate. The time taken to

load this external buffer must be at least equal to the sum of

the time to transfer data in and out of the FFT processor and

the transform time itself. When data blocks are overlapped by

50% or 75%, no more than one half or one quarter of the block,

respectively, must have been loaded in the same time. In the

1024 point modes the dump time can be any user defined

value, and need not be increased to allow for block

overlapping. The dump time, however , does directly effect the

maximum sampling rates which can be accommodated

without loss of incoming data.

The maximum sampling rates for 1024 point transforms at any

load and dump rate can be calculated from the following

relationship:

1024S or 512S or 256S > 1024B + PK + D

for 0%, 50%, or 75% overlapping respectively. S, P, and K

were defined opposite. B is the clock period in which data is

read from the input buffer and loaded into the device, D is the

total dump time allowing for the four extra DOS periods. The

periods of the load and dump clocks cannot be less than the

system clock period. The maximum sampling rates given in

Figure 7. Multiple Device Configuration

REAL

O/P

PDSP16515

IMAG

PDSP16330

REAL

O/P

PDSP16515

IMAG

REAL

O/P

PDSP16515

IMAG

Complex Data

Input

Configuration

Parameters

Power on

Reset

Output

Clock

CLK

PHASE

MAG'

SCALE

TAG

DATA

AVAIL'

INPUT CLOCK

GND

PDSP16515GCPR Datasheet(PDF) 14 Page - Mitel Networks Corporation

PDSP16515GCPR Datasheet(HTML) 14 Page - Mitel Networks Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Datasheet Download

Link URL