LM95233CISDXSLASHNOPB datasheet(7/44 Pages) TI

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VIH

VIL

SMBCLK

VIH

VIL

SMBDAT

tBUF

tHD;STA

tLOW

tHD;DAT

tHIGH

tSU;DAT

tSU;STA

tSU;STO

LM95233

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SNIS145E – AUGUST 2006 – REVISED MARCH 2013

SMBus DIGITAL SWITCHING CHARACTERISTICS

Unless otherwise noted, these specifications apply for VDD=+3.0 Vdc to +3.6 Vdc, CL (load capacitance) on output lines =

80 pF. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless otherwise noted.

The switching characteristics of the LM95233 fully meet or exceed the published specifications of the SMBus version 2.0. The

following parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM95233. They

adhere to but are not necessarily the SMBus bus specifications.

Typical(1)

Limits(2)

Units

Symbol

Parameter

Conditions

(Limit)

fSMB

SMBus Clock Frequency

100

kHz (max)

kHz (min)

tLOW

SMBus Clock Low Time

from VIN(0)max to VIN(0)max

4.7

µs (min)

ms (max)

tHIGH

SMBus Clock High Time

from VIN(1)min to VIN(1)min

4.0

µs (min)

tR,SMB

SMBus Rise Time

(3)

µs (max)

tF,SMB

SMBus Fall Time

(4)

0.3

µs (max)

tOF

Output Fall Time

CL = 400 pF,

250

ns (max)

IO = 3 mA,

(4)

tTIMEOUT

SMBDAT and SMBCLK Time Low for Reset of

ms (min)

Serial Interface (5)

ms (max)

tSU;DAT

Data In Setup Time to SMBCLK High

250

ns (min)

tHD;DAT

Data Out Stable after SMBCLK Low

300

ns (min)

1075

ns (max)

tHD;STA

Start Condition SMBDAT Low to SMBCLK Low

100

ns (min)

(Start condition hold before the first clock falling

edge)

tSU;STO

Stop Condition SMBCLK High to SMBDAT Low

100

ns (min)

(Stop Condition Setup)

tSU;STA

SMBus Repeated Start-Condition Setup Time,

0.6

µs (min)

SMBCLK High to SMBDAT Low

tBUF

SMBus Free Time Between Stop and Start

1.3

µs (min)

Conditions

(1)

Typicals are at TA = 25°C and represent most likely parametric norm.

(2)

Limits are specified to AOQL (Average Outgoing Quality Level).

(3)

The output rise time is measured from (VIN(0)max − 0.15V) to (VIN(1)min + 0.15V).

(4)

The output fall time is measured from (VIN(1)min + 0.15V) to (VIN(0)max − 0.15V).

(5)

Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the LM95233's SMBus state machine,

therefore setting SMBDAT and SMBCLK pins to a high impedance state.

Figure 2. SMBus Communication

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