286C6116FSC datasheet(42/46 Pages) ZILOG

42 / 46 page

Z86C61/62/96

Z8® MICROCONTROLLER

INSTRUCTION SUMMARY (Continued)

Address

Instruction

Mode

Opcode

Flags Affected

and Operation

dst src

Byte (Hex) C Z S V D H

NOP

OR dst, src

†

4[ ]

TT 0-

dst

←dst OR src

POP dst

dst

←@SP;

←SP + 1

PUSH src

←SP – 1;

@SP

←src

RCF

←0

RET

←@SP;

←SP + 2

RL dst

TT TT --

RLC dst

TT TT --

RR dst

TT TT --

RRC dst

TT TT --

SBC dst, src

†

3[ ]

TT TT 1 T

dst

←dst←src←C

SCF

←1

SRA dst

TT T 0-

SRP src

←src

Address

Instruction

Mode

Opcode

Flags Affected

and Operation

dst src

Byte (Hex) C Z S V D H

STOP

SUB dst, src

†

2[ ]

TT TT 1 T

dst

←dst←src

SWAP dst

X TT X-

TCM dst, src

†

6[ ]

TT 0-

(NOT dst)

AND src

TM dst, src

†

7[ ]

TT 0-

dst AND src

XOR dst, src

†

B[ ]

TT 0-

dst

←dst

XOR src

† These instructions have an identical set of addressing modes, which

are encoded for brevity. The first opcode nibble is found in the instruction

set table above. The second nibble is expressed symbolically by a ‘[ ]’

in this table, and its value is found in the following table to the left of the

applicable addressing mode pair.

For example, the opcode of an ADC instruction using the addressing

modes r (destination) and Ir (source) is 13.

Address Mode

Lower

dst

src

Opcode Nibble

[2]

[3]

[4]

[5]

[6]

[7]

286C6116FSC Datasheet(PDF) 42 Page - Zilog, Inc.

286C6116FSC Datasheet(HTML) 42 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Datasheet Download

Link URL