26 / 62 page
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *C
Page 26 of 62
CY37128
CY37192
Typical 5.0V Power Consumption (continued)
0
20
40
60
80
100
120
140
160
0
2 0
4 0
6 0
8 0
100
120
140
160
180
Fre q ue n c y (M Hz )
Lo w P o w e r
H ig h S p eed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
0
50
100
150
200
250
300
0
2 0
4 0
6 0
8 0
100
120
140
160
180
Fre q ue n c y (M Hz )
Low P o w e r
Hig h S p e e d
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 5.0V, TA = Room Temperature
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
