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M24C16-DFCU6TP Datasheet(PDF) 27 Page - STMicroelectronics

Part # M24C16-DFCU6TP
Description  16-Kbit serial I²C bus EEPROM 4 balls CSP
PDF  35 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M24C16-DFCU6TP Datasheet(HTML) 27 Page - STMicroelectronics

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M24C16-DFCU
DC and AC parameters
34
Table 12. 400 kHz AC characteristics
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock frequency
-
400
kHz
tCHCL
tHIGH
Clock pulse width high
600
-
ns
tCLCH
tLOW
Clock pulse width low
1300
-
ns
tQL1QL2(1)
1. Characterized only, not tested in production.
tF
SDA (out) fall time
20
120
ns
tXH1XH2
tR
Input signal rise time
(2)
2. There is no min. or max. value for the input signal rise and fall times. It is however recommended by the I²C
specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
(2)
ns
tXL1XL2
tF
Input signal fall time
(2)
(2)
ns
tDXCH
tSU:DAT Data in set up time
100
-
ns
tCLDX
tHD:DAT Data in hold time
0
-
ns
tCLQX (3)
3. The min value for tCLQX (Data out hold time) offers a safe timing to bridge the undefined region of the falling
edge SCL.
tDH
Data out hold time
100
-
ns
tCLQV (4)
4. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is less than 400 ns.
tAA
Clock low to next data valid (access time)
-
900
ns
tCHDL
tSU:STA Start condition setup time
600
-
ns
tDLCL
tHD:STA Start condition hold time
600
-
ns
tCHDH
tSU:STO Stop condition set up time
600
-
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
-
ns
tW
tWR
Write time
-
5
ms
tNS(1)
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-80
ns



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