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SAFC165UTAH Datasheet(PDF) 39 Page - Infineon Technologies AG

Part # SAFC165UTAH
Description  EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT
PDF  539 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

SAFC165UTAH Datasheet(HTML) 39 Page - Infineon Technologies AG

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C165UTAH
Architectural Overview
Data Sheet
39
2001-02-23
Table 10
C165UTAH Clock Generation Modes
PLL Operation
On power-up the PLL provides a stable clock signal within ca. 1 ms after VDD has
reached 3.3 V
±10%, even if there is no external clock signal (in this case the PLL will run
on its basic frequency of 2...5 MHz). The PLL starts synchronizing with the external clock
signal as soon as it is available. Within ca. 1 ms after stable oscillations of the external
clock within the specified frequency range the PLL will be synchronous with this clock at
a frequency of F *fOSC, ie. the PLL locks to the external clock.
Note: If the C165UTAH is required to operate on the desired CPU clock directly after
reset make sure that RSTIN remains active until the PLL has locked (ca. 1 ms).
When PLL operation is selected the CPU clock is a selectable multiple of the oscillator
frequency, ie. the input frequency. The table above lists the possible selections.
P0H.7-P0H.5 Frequency
Divider Activation
USB Interface is NOT used
001
f
XTAL * 0.5
direct drive, D1 not active, D2 active, PLL free running (2..5 MHZ)
Note: The PLL can be switched off completely by setting bit
PLLDIS = ’1’ (SYSCON3.13, see page 470).
010
fXTAL * 1.5
D1 not active, D2 not active, F = 1.5
011
f
XTAL * 1.0
direct drive, D1 not active, D2 not active, PLL free running (2..5
MHz)
Note: The PLL can be switched off completely by setting bit
PLLDIS = ’1’ (SYSCON3.13, see page 470).
100
fXTAL * 6.0
D1 not active, D2 not active, F = 6.0
101
f
XTAL * 1.125
D1 active, D2 active, F = 1.125
110
f
XTAL * 3.0
D1 not active, D2 not active, F = 3.0
111
f
XTAL * 4.5
D1 not active, D2 not active, F = 4.5, Default Mode
000
f
XTAL * 0.375
D1 active, D2 active, F = 0.375
USB Interface is used (USB clock must be 48 MHz)
110
fXTAL * 3
D1 not active, D2 not active, F = 3.0
f
USB =
def 48 MHz
Τ f
XTAL = 8 MHz
Τ f
CPU = 24 MHz
111
f
XTAL * 4.5
D1 not active, D2 not active, F = 4.5, Default Mode
f
USB =
def 48 MHz
Τ f
XTAL = 8 MHz
Τ f
CPU = 36 MHz



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