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SAFC165UTAH Datasheet(PDF) 21 Page - Infineon Technologies AG

Part # SAFC165UTAH
Description  EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT
PDF  539 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

SAFC165UTAH Datasheet(HTML) 21 Page - Infineon Technologies AG

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C165UTAH
Pin Descriptions
Data Sheet
21
2001-02-23
117-121,
124-126
P6.0-
P6.7
O
I/O
O
...
O
I
O
O
Port6 is an 8-bit bidirectional I/O port. It is bit-
wise programmable for input or output via
direction bits. For a pin configured as input, the
output driver is put into high-impedance state.
Port6 outputs can be configured as push/pull
or open-drain drivers.
P6.0
CS0
Chip Select 0 Output
...
...
...
P6.4
CS4
Chip Select 4 Output
P6.5
HOLD
External Master Hold
Request Input
P6.6
HLDA
Hold Acknowledge Output
P6.7
BREQ
Bus Request Output
131-134,
137-140
P2.0-
P2.7
I/O
I
I
PORT2 is an 8-bit bidirectional I/O port. It is
bit-wise programmable for input or output via
direction bits. For a pin configured as input, the
output driver is put into high-impedance state.
Port2 outputs can be configured as push/pull
or open-drain drivers.
P2.0
EX0IN
Fast External Interrupt 0
Input
P2.7
EX7IN
Fast External Interrupt 7
Input
53
RD
O
External Memory Read Strobe. RD is
activated for every external instruction or data
read access.
54
WR/WRL O
External Memory Write Strobe. In WR mode
this pin is activated for every external data
write access. In WRL mode this pin is
activated for low byte data write accesses on a
16-bit bus, and for every data write access on
an 8-bit bus. See WRCFG in register
SYSCON for mode selection.
56
ALE
O
Address Latch Enable Output. Can be used for
latching the address into external memory or
an address latch in the multiplexed bus
modes.
Table 2
Microprocessor Bus and Control Signals
Pin No.
Symbol
Input (I)
Output (O)
Function



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