SAFC165UTAH datasheet(13/539 Pages) INFINEON

13 / 539 page

C165UTAH

Overview

Data Sheet

2001-02-23

• USB Interface including:

– USB Specification 1.1 Compliant

– 12 Mbit/s Full-Speed Mode

– 7SW-configurable Endpoints, in addition to the bi-directional Control Endpoint 0

– 3 Configurations with 3 alternate settings and 4 interfaces supported

– Each non-Control Endpoint can be either Isochronous, Bulk or Interrupt

– Autonomous DMA Transfer by on-chip DMA for 8 USB endpoints

• ISDN Terminal Adapter Features including:

– Four Independent Full-Duplex HDLC Controllers

– IOM-2/PCM interface supporting TE, LT and PCM mode

– MON and CI1/CI2-Handler

– Two D-Channels

– Two B-Channels Supported

– Concatenated 2B+D channel Support

– Two Intercommunication Channels IC1, IC2

– D-Channel Access Control to first IOM channel-0 by S/G bit

– CDA Channel Access to individual IOM-2/PCM channels by SW

• On-Chip PLL for CPU and USB clock generation

• External crystal and direct driven input clock of 8 MHz when USB interface is used. In

applications without USB, the input clock frequency can vary between 4 and 20 MHz

dependent on the CPU target clock frequency.

• Single and variable crystal clock input frequency (using USB 8 MHz only)

• Bootstrap Loader support via USART interface

• On-Chip Debug Support (OCDS)

• JTAG Boundary Scan Test support according to IEEE 1149.1

• 3.3 V single supply voltage

• 5 V (TTL-) tolerant I/Os

• C165UTAH is available in 144-Pin P-TQFP package

SAFC165UTAH Datasheet(PDF) 13 Page - Infineon Technologies AG