PEB2256HT datasheet(36/490 Pages) INFINEON

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FALC56 V1.2

PEB 2256

Pin Descriptions

Data Sheet

2002-08-27

•

Table 3

Pin Definitions - Clock Generation

No.

Symbol

Input (I)

Output (O)

Supply (S)

Function

MCLK

Master Clock

A reference clock of better than ± 32 ppm

accuracy in the range of 1.02 to 20 MHz must

be provided on this pin. The FALC®56

internally derives all necessary clocks from this

master

(see registers GCM(6:1)).

SYNC

I + PU

Clock Synchronization of DCO-R

If a clock is detected on pin SYNC the

DCO-R circuitry of the FALC

®56 synchronizes

to this 1.544/2.048 MHz clock (see LIM0.MAS,

CMR1.DCS and CMR2.DCF). Additionally, in

master mode the FALC

®56 is able to

synchronize to an 8-kHz reference clock

(IPC.SSYF = 1). If not connected, an internal

pullup transistor ensures high input level.

CLK1

O + PU

System Clock of DCO-R

Output of the de-jittered system clock

generated by the DCO-R circuit. Frequency

selection is done by setting control bits in PC5/

E1: 16.384 MHz, 8.192 MHz, 4.096 MHz,

2.048 MHz or 8 kHz

T1/J1: 16.384 MHz, 12.352 MHz, 8.192 MHz,

6.176 MHz, 4.096 MHz, 3.088 MHz, 2.048

MHz, 1.544 MHz or 8 kHz

After reset this output is inactive and internally

pulled high.

Note: If DCO-R is not active, no clock is output

on pin CLK1 (SIC1.RBS(1:0) = 11 and

CMR1.RS1 = 0).

PEB2256HT Datasheet(PDF) 36 Page - Infineon Technologies AG

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