3

36-00-01-00

5

Ver. 1.0.0

Aeroflex Microelectronics Solutions - HiRel

Table 1: Pin Definitions

NAME

DESCRIPTION

TYPE

CS0

Chip Enable 0, Input, Active LOW: Sampled on the rising edge of CLK.

Used in conjunction with CS1 and CS2 to select or deselect the device.

Input-Synchronous

CS1

Chip Enable 1 Input, Active HIGH: Sampled on the rising edge of CLK.

Used in conjunction with CS0 and CS2 to select or deselect the device.

Input-Synchronous

CS2

Chip Enable 2 Input, Active LOW: Sampled on the rising edge of CLK.

Used in conjunction with CS0 and CS1 to select or deselect the device.

Input-Synchronous

A[20:0]

Address Inputs: Sampled at the rising edge of the CLK. A[1:0] is fed to the

two-bit burst counter.

Input-Synchronous

BWE[4:0]

Byte Write Enable, Active LOW: Qualified with WE, allows writes to each

of six bytes of memory when active, and masks input data when disabled.

Input-Synchronous

WE

Write Enable Input, Active LOW: Sampled on the rising edge of CLK if

CEN is active LOW. This signal must be enabled LOW to initiate a write

sequence.

Input-Synchronous

ADV_LD

Advance/Load Input: Advances the on-chip address counter or loads a new

address. When HIGH (and CEN is enabled LOW) the internal burst counter

is advanced. When LOW, a new address can be loaded into the device for an

access. After deselection, drive ADV_LD LOW to load a new address.

Input-Synchronous

CLK

Clock Input: Used to capture all synchronous inputs to the device. CLK is

qualified with CEN. CLK is only recognized if CEN is active LOW.

Input-Clock

OE

Output Enable, Asynchronous Input, Active LOW: Combined with the

synchronous logic block inside the device to control the direction of the I/O

pins. When LOW, the I/O pins are enabled to behave as outputs. When

disabled HIGH, I/O pins are tri-stated, and act as input data pins. OE is

masked during the data portion of a write sequence, during the first clock

when emerging from a deselected state and when the device is deselected.

Input-Asynchronous

CEN

Clock Enable Input, Active LOW: When enabled LOW, the clock signal is

recognized by the SSRAM. When deasserted HIGH, the clock signal is

masked. Because deasserting CEN does not deselect the device, CEN can be

used to extend the previous cycle when required.

Input-Synchronous

DQ[47:0]

Bidirectional Data I/Os: As inputs, DQ[47:0] feed into an on-chip data

register that is triggered by the rising edge of CLK. As outputs, DQ[47:0]

delivers the data contained in the memory location specified by the addresses

presented during the previous clock rise of the read cycle. The direction of

the pins is controlled by OE. When OE is enabled LOW, the pins behave as

outputs. When HIGH, DQs are placed in a tri-state condition. The outputs

are automatically tri-stated during the data portion of a write sequence,

during the first clock when emerging from a deselected state, and when the

device is deselected, regardless of the state of OE. Aeroflex recommends

connecting all DQ pins to either VDDQ or VSS through a >10kΩ resistor.

I/O-Synchronous

RESET

Reset Input, Active Low: Resets device to known configuration. Reset is

required at initial power-up, after exiting shutdown mode, or after any power

interruption.

Input-ASynchronous